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ZSC31015EEG1-R 数据表(PDF) 7 Page - Integrated Device Technology |
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ZSC31015EEG1-R 数据表(HTML) 7 Page - Integrated Device Technology |
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7 / 52 page ![]() © 2016 Integrated Device Technology, Inc 7 November 14, 2016 ZSC31015 Datasheet 1 Electrical Characteristics 1.1. Absolute Maximum Ratings Note: The absolute maximum ratings are stress ratings only. The device might not function or be operable above the operating conditions given in section 1.2. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. IDT does not recommend designing to the “Absolute Maximum Ratings.” Parameter Symbol Min Max Unit Analog Supply Voltage VDD -0.3 6.0 V Voltages at Analog I/O – In Pin VINA -0.3 VDD+0.3 V Voltages at Analog I/O – Out Pin VOUTA -0.3 VDD+0.3 V Storage Temperature Range ( 10 hours) TSTOR -50 150 °C Storage Temperature Range (<10 hours) TSTOR <10h -50 170 °C Note: Also see Table 6.1 regarding soldering temperature and storage conditions. 1.2. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Analog Supply Voltage to Ground VDD 2.7 5.0 5.5 V Analog Supply Voltage (with external JFET Regulator) VSUPP 5.5 7 30 V Common Mode Voltage VCM 1 VDD – 1.3 V Ambient Temperature Range 1), 2) TAMB -50 150 C External Capacitance between VDD and Ground CVDD 100 220 470 nF Output Load Resistance to VDD 3) RL,OUT 5 k Output Load Resistance to VSS 3),4) RL,OUT 5 k Output Load Capacitance 5) CL,OUT 1 10 15 nF Bridge Resistance 6),7) RBR 0.3 100 k Power-On Rise Time tPON 100 ms 1) Note that the maximum EEPROM programming temperature is 85°C. 2) If buying die, designers should use caution not to exceed maximum junction temperature by proper package selection. 3) Only needed for Analog Output Mode; not needed for Digital Output Mode. When a pull-down resistor is used as the load resistor, the power loss detection diagnostic for loss of VSS cannot be assured at RL=5k; RL=10k is recommended for this configuration. 4) Note: for unlocked devices or during calibration, the minimum value of output load resistance to VSS is 20k Ω. 5) Using the output for digital calibration, CL,OUT is limited by the maximum rise time tZAC,rise. See section 1.3.8. 6) Note: Minimum bridge resistance is a factor if using the Bsink feature. The rds(on) of the Bs ink transistor is 8 to 10Ω when operating at V DD=5V. This does give rise to a ratiometricity inaccuracy that becomes greater with low bridge resistances. 7) Note: Minimum bridge resistance is important if using certain diagnostic features. It must be at least 0.3k Ω at V DD=2.7V and at least 0.6kΩ at VDD=5V for the Sensor Short Check to function properly. For details, see section 2.6.3. |
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