X9521 datasheet(13/26 Pages) XICOR

13 / 26 page

REV 1.1.9 1/30/03

Characteristics subject to change without notice.

13 of 26

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X9521

– Preliminary Information

The region of EEPROM memory which is protected /

locked is determined by the combination of the BL1 and

BL0 bits written to the CONSTAT register. It is possible to

lock the regions of EEPROM memory shown in the table

below:

If the user attempts to perform a write operation on a pro-

tected region of EEPROM memory, the operation is

aborted without changing any data in the array.

When the Block Lock bits of the CONSTAT register are

set to something other than BL1=0 and BL0=0, then the

“wiper position” of the DCPs cannot be changed - i.e.

DCP write operations cannot be conducted:

The factory default setting for these bits are BL1 = 0, BL0

= 0.

IMPORTANT NOTE: If the Write Protect (WP) pin of the

X9521 is active (HIGH), then all nonvolatile write opera-

tions to both the EEPROM memory and DCPs are inhib-

ited, irrespective of the Block Lock bit settings (See "WP:

Write Protection Pin").

CONSTAT Register Write Operation

The CONSTAT register is accessed using the Slave

Address set to 1010010 (Refer to Figure 4.). Following the

Slave Address Byte, access to the CONSTAT register

requires an Address Byte which must be set to FFh. Only

one data byte is allowed to be written for each CONSTAT

after sending this byte to the register, to initiate the nonvol-

atile cycle that stores the BP1and BP0 bits. The X9521

will not ACKNOWLEDGE any data bytes written after the

ﬁrst byte is entered (Refer to Figure 18.).

When writing to the CONSTAT register, the bits CS7-CS5

and CS0 must all be set to “0”. Writing any other bit

sequence to bits CS7-CS5 and CS0 of the CONSTAT

Prior to writing to the CONSTAT register, the WEL and

RWEL bits must be set using a two step process, with the

whole sequence requiring 3 steps

—Write a 02H to the CONSTAT Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation preceded by

a START and ended with a STOP).

—Write a 06H to the CONSTAT Register to set the Regis-

ter Write Enable Latch (RWEL) AND the WEL bit. This

is also a volatile cycle. The zeros in the data byte are

required. (Operation preceded by a START and ended

with a STOP).

—Write a one byte value to the CONSTAT Register that

has all the bits set to the desired state. The CONSTAT

where st are the Block Lock Protection (BL1 and BL0)

bits. This operation is proceeded by a START and

ended with a STOP bit. Since this is a nonvolatile write

cycle, it will typically take 5ms to complete. The RWEL

bit is reset by this cycle and the sequence must be

repeated to change the nonvolatile bits again. If bit 2 is

set to ‘1’ in this third step (000s t110) then the RWEL bit

is set, but the BL1 and BL0 bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and the

X9521 does not return an ACKNOWLEDGE.

BL1 BL0

Protected Addresses

(Size)

Partition of array

locked

None (Default)

C0h - FFh (64 bytes)

Upper 1/4

80h - FFh (128 bytes)

Upper 1/2

00h - FFh (256 bytes)

All

BL1

BL0

DCP Write Operation Permissible

YES (Default)

R/W A

SCL

SDA

CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0

SLAVE ADDRESS BYTE

ADDRESS BYTE

CONSTAT REGISTER DATA IN

Figure 18. CONSTAT Register Write Command Sequence

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