X9521 datasheet(4/26 Pages) XICOR

4 / 26 page

REV 1.1.9 1/30/03

Characteristics subject to change without notice.

4 of 26

www.xicor.com

X9521

– Preliminary Information

nate further data transmissions if an ACKNOWLEDGE is

not detected. The master must then issue a STOP condi-

tion to place the device into a known state.

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

The user addressable internal components of the X9521

can be split up into three main parts:

—Two Digitally Controlled Potentiometers (DCPs)

—EEPROM array

—Control and Status (CONSTAT) Register

Depending upon the operation to be performed on each

of these individual parts, a 1, 2 or 3 Byte protocol is used.

All operations however must begin with the Slave Address

Byte being issued on the SDA pin. The Slave address

selects the part of the X9521 to be addressed, and speci-

ﬁes if a Read or Write operation is to be performed.

It should be noted that in order to perform a write opera-

tion to either a DCP or the EEPROM array, the Write

Enable Latch (WEL) bit must ﬁrst be set (See “BL1, BL0:

Block Lock protection bits - (Nonvolatile)” on page 12.)

Slave Address Byte

Following a START condition, the master must output a

Slave Address Byte (Refer to Figure 4.). This byte con-

sists of three parts:

—The Device Type Identiﬁer which consists of the most

signiﬁcant four bits of the Slave Address (SA7 - SA4).

The Device Type Identiﬁer must always be set to 1010

in order to select the X9521.

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally selects

the EEPROM array, while setting these bits to 111

selects the DCP structures in the X9521. The CON-

STAT Register may be selected using the Internal

Device Address 010.

—The Least Signiﬁcant Bit of the Slave Address (SA0)

Byte is the R/W bit. This bit deﬁnes the operation to be

performed on the device being addressed (as deﬁned

in the bits SA3 - SA1). When the R/W bit is “1”, then a

READ operation is selected. A “0” selects a WRITE

operation (Refer to Figure 4.)

SCL

from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start

Acknowledge

Figure 3.

Acknowledge Response From Receiver

SCL

from

Master

SA6

SA7

SA5

SA3

SA2

SA1

SA0

DEVICE TYPE

IDENTIFIER

READ /

SA4

Internal Address

(SA3 - SA1)

Internally Addressed

Device

000

EEPROM Array

010

CONSTAT Register

111

DCP

Bit SA0

Operation

WRITE

READ

R/W

Figure 4.

Slave Address Format

101

WRITE

ADDRESS

INTERNAL

DEVICE

X9521 数据表(PDF) 4 Page - Xicor Inc.

X9521 数据表(HTML) 4 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表下载

链接网址

X9521 数据表(PDF) 4 Page - Xicor Inc.

X9521 数据表(HTML) 4 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表 下载

链接网址

数据表下载