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L9950

4.3

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at

the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the

CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the

selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication

frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be

ignored. This safety function is implemented to avoid an activation of the output stages by a wrong com-

munication frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling

the CSN signal of the connected ICs is recommended.

4.4

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance

to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input

after a high to low transition of the CSN pin will transfer the content of the selected status register into the

data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

4.5

Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sam-

pled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK

signal.

4.6

Input Data Register

The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two Input

Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of

the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data

bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO

during the current communication frame. Bit 1-17 controls the behaviour of the corresponding driver.

If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to control the current

monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status

registers will be cleared after the current communication frame (rising edge of CSN).

4.7

Status Register

This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a

fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be

polled by the microcontroller without the need of a full SPI-communication cycle (see FIGURE 11). If one

of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of

the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal

shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear

the bit to enable the drivers.

4.8

Test Mode

The Test Mode can be entered by rising the CSN input to a voltage higher than 7.0V. In the test mode the

inputs CLK, DI, PWM1/2 and the internal 2MHz CLK can be multiplexed to data output DO for testing pur-

pose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower

current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW

and TSD thresholds.

The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched-

on at the same time. In the testmode this combination is used to multiplex the desired signals according

to following table 8: