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L9950

Table 2. Pin Description

Pin

Symbol

Function

1, 18, 19,

36

GND

Ground:

Reference potential

Important: For the capability of driving the full current at the outputs all pins of GND must

be externally connected !

2.35

OUT11

Highside-driver-output 11:

The output is built by a highside switch and is intended for resistive loads, hence the

internal reverse diode from GND to the output is missing. For ESD reason a diode to GND

is present but the energy which can be dissipated is limited. The highside driver is a power

DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-

diode). The output is over-current and open load protected.

Important: For the capability of driving the full current at the outputs both pins of OUT11

must be externally connected !

3

4

5

OUT1

OUT2

OUT3

Halfbridge-output 1,2,3:

The output is built by a highside and a lowside switch, which are internally connected. The

output stage of both switches is a power DMOS transistor. Each driver has an internal

parasitic reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver

from GND to output). This output is over-current and open load protected.

6, 7, 14, 15,

23, 24, 25,

28, 29, 32

VS

Power supply voltage (external reverse protection required):

For this input a ceramic capacitor as close as possible to GND is recommended.

Important: For the capability of driving the full current at the outputs all pins of VS must be

externally connected !

8DI

Serial data input:

The input requires CMOS logic levels and receives serial data from the microcontroller.

The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred

first.

9CM/PWM2

Current monitor output/PWM2 input:

Depending on the selected multiplexer bits of Input Data Register this output sources an

image of the instant current through the corresponding highside driver with a ratio of 1/

10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor

signal to provide a second PWM input for the outputs OUT9 and OUT10.

10

CSN

Chip Select Not input / Testmode :

This input is low active and requires CMOS logic levels. The serial data transfer between

L9950 and micro controller is enabled by pulling the input CSN to low level. If an input

voltage of more than 7.5V is applied to CSN pin the L9950 will be switched into a test

mode.

11

DO

Serial data output:

The diagnosis data is available via the SPI and this tristate-output. The output will remain

in tristate, if the chip is not selected by the input CSN (CSN = high)

12

VCC

Logic supply voltage:

For this input a ceramic capacitor as close as possible to GND is recommended.

13

CLK

Serial clock input:

This input controls the internal shift register of the SPI and requires CMOS logic levels.

16,17,

20,21,

22

OUT4

OUT5

OUT6

Halfbridge-output 4,5,6:

Important: For the capability of driving the full current at the outputs both pins of OUT4

(OUT5, respectively) must be externally connected !

26

CP

Charge Pump Output:

This output is provided to drive the gate of an external n-channel power MOS used for

reverse polarity protection (see FIGURE 1)

27

PWM1

PWM1 input:

This input signal can be used to control the drivers OUT1-OUT8 and OUT11 by an

external PWM signal.

30

31

33

34

OUT7,

OUT8,

OUT9,

OUT10

Highside-driver-output 7,8,9,10:

The output is built by a highside switch and is intended for resistive loads, hence the

internal reverse diode from GND to the output is missing. For ESD reason a diode to GND

is present but the energy which can be dissipated is limited. The highside driver is a power

DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-

diode). The output is over-current and open load protected.