ADE7754 datasheet(14/44 Pages) AD

14 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 14 –

In addition to the MASK bits, the Zero crossing detection

interrupt of each phase is enabled/disabled by setting the

ZXSEL bits of the MMODE register (Addr. 0x0B) to logic

one or zero respectively.

Zero crossing Time out

Each zero crossing detection has an associated internal time-

out register (not accessible to the user). This unsigned,

16-bit register is decremented (1 LSB) every 384/CLKIN

seconds. The registers are reset to a common user pro-

grammed value -i.e. Zero Cross Time Out register

(ZXTOUT, Addr. 0x12) every time a zero crossing is

detected on its associated input. The default value of ZXTOUT

is FFFFh. If the internal register decrements to zero before

a zero crossing at the corresponding input is detected, it

indicates an absence of a zero crossing in the time determined

by the ZXTOUT. The ZXTO detection bit of the corre-

sponding phase in the Interrupt Status Register is then

switched on (bit 4-6). An active-low on the IRQ output will

also appear if the SAG mask bit for the corresponding phase

in the Interrupt Mask register is set to logic one.

In addition to the MASK bits, the Zero crossing Time out

detection interrupt of each phase is enabled/disabled by

setting the ZXSEL bits of the MMODE register (Addr.

0x0B) to logic one or zero respectively. When the zero

crossing Time out detection is disabled by this method, the

ZXTO flag of the corresponding phase is switched ON all the

time.

Figure 13 shows the mechanism of the zero crossing time out

detection when the line voltage A stays at a fixed DC level for

more than CLKIN/384 x ZXTOUT seconds.

Voltage

channel A

ZXTOA

detection bit

ZXTOUT

16-bit internal

Figure 13 - Zero crossingTime out detection

PERIOD MEASUREMENT

The ADE7754 provides also the period measurement of the

line voltage. The period is measured on the phase specified

by bit 0-1 of the MMODE register. The period register is an

unsigned 15-bit register and is updated every period of the

selected phase. Bit 0-1 and bit 4-6 of the MMODE register

select the phase for the period measurement, both selection

should indicate the same phase. The ZXSEL bits of the

MMODE register (bit 4-6) enable the phases on which the

Period measurement can be done. The PERDSEL bits select

the phase for Period measurement within the phases selected

by the ZXSEL bits.

The resolution of this register is 2.4

µs/LSB when

CLKIN=10MHz, which represents 0.014% when the line

frequency is 60Hz. When the line frequency is 60Hz, the

value of the Period register is approximately 6944d. The

length of the register enables the measurement of line

frequencies as low as 12.7Hz.

LINE VOLTAGE SAG DETECTION

The ADE7754 can be programmed to detect when the

absolute value of the line voltage of any phase drops below a

certain peak value, for a number of half cycles. Each phase of

the voltage channel is controlled simultaneously. This con-

dition is illustrated in Figure 14 below.

SAGCYC[7:0] = 06h

6 half cycles

SAGLVL[7:0]

Full Scale

VAP, VBP, or VCP

SAG Interrupt Flag

(Bit 1 to 3 of STATUS register)

SAG event reset low

when voltage channel

exceeds SAGLVL[7:0]

Read RSTATUS register

Figure 14 – ADE7754 Sag detection

Figure 14 shows a line voltage falling below a threshold

which is set in the Sag Level register (SAGLVL[7:0]) for

nine half cycles. Since the Sag Cycle register indicates a 6

half-cycle threshold (SAGCYC[7:0]=06h), the SAG event is

recorded at the end of the sixth half-cycle by setting the SAG

flag of the corresponding phase in the Interrupt status register

(bit 1 to 3 in the Interrupt Status register). If the SAG enable

bit is set to logic one for this phase (bit 1 to 3 in the Interrupt

Mask register), the IRQ logic output will go active low - see

ADE7754 Interrupts. All the phases are compared to the same

parameters defined in the SAGLVL and SAGCYC registers.

Sag Level Set

The content of the Sag Level register (1 byte) is compared to

the absolute value of the most significant byte output from the

voltage channel ADC. Thus, for example, the nominal

maximum code from the voltage channel ADC

with a full

scale signal is 28F5h —see Voltage Channel Sampling.

Therefore, writing 28h to the Sag Level register will put the

sag detection level at full scale and set the SAG detection to

its most sensitive value.

Writing 00h will put the Sag detection level at zero. The

detection of a decrease of an input voltage is in this case

hardly possible. The detection is made when the content of

the SAGLVL register is greater than the incoming sample.

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