ADE7754 datasheet(16/44 Pages) AD

16 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 16 –

PHASE COMPENSATION

When the HPFs are disabled the phase error between the

current channel (IA, IB and IC) and the voltage channel (VA,

VB and VC) is zero from DC to 3.3kHz. When the HPFs are

enabled, the current channels

have a phase response illus-

trated in Figure 16a & 16b. Also shown in Figure 16c is the

magnitude response of the filter. As can be seen from the

plots, the phase response is almost zero from 45Hz to 1kHz,

This is all that is required in typical energy measurement

applications.

-0.01

0.01

0.02

0.03

0.04

0.05

0.06

0.07

100

200

300

400

500

600

700

800

900 1000

Frequency (Hz)

Phase

(Degree)

Figure 16a – Phase response of the HPF & Phase

Compensation (10Hz to 1kHz)

-0.004

-0.002

0.002

0.004

0.006

0.008

0.01

Frequency (Hz)

Phase

(Degree)

Figure 16b - Phase response of the HPF & Phase

compensation (40Hz to 70Hz)

-0.004

-0.002

0.002

0.004

0.006

0.008

0.01

Frequency (Hz)

Phase

(Degree)

Figure 16c – Gain response of HPF & Phase Compensation

(deviation of Gain as % of Gain at 54Hz)

However despite being internally phase compensated, the

ADE7754 must work with transducers which may have

inherent phase errors. For example a phase error of 0.1° to

0.3° is not uncommon for a CT (Current Transformer).

These phase errors can vary from part to part and they must

be corrected in order to perform accurate power calculations.

The errors associated with phase mismatch are particularly

noticeable at low power factors. The ADE7754 provides a

means of digitally calibrating these small phase errors. The

ADE7754 allows a small time delay or time advance to be

introduced into the signal processing chain in order to

compensate for small phase errors. Because the compensa-

tion is in time, this technique should only be used for small

phase errors in the range of 0.1° to 0.5°. Correcting large

phase errors using a time shift technique can introduce

significant phase errors at higher harmonics.

The Phase Calibration registers (APHCAL, BPHCAL and

CPHCAL) are 2’s complement 5-bit signed registers which

can vary the time delay in the voltage channel signal path from

–19.2µs to +19.2µs (CLKIN = 10MHz). One LSB is

equivalent to 1.2µs. With a line frequency of 50Hz this gives

a phase resolution of 0.022° at the fundamental (i.e., 360° x

1.2µs x 50Hz).

Figure 17 illustrates how the phase compensation is used to

remove a 0.091° phase lead in IA of the current channel due

to some external transducer. In order to cancel the lead

(0.091°) in IA of the current channel, a phase lead must also

be introduced into VA of the voltage channel. The resolution

of the phase adjustment allows the introduction of a phase

lead of 0.086°. The phase lead is achieved by introducing a

time advance into VA. A time advance of 4.8µs is made by

writing -4 (1Ch) to the time delay block (APHCAL[4:0]),

thus reducing the amount of time delay by 4.8µs - see

Calibration of a 3-phase meter based on the ADE7754.

VAP

ADC

PGA2

LPF2

HPF

IAP

IAN

ADC

PGA1

APHCAL[4:0]

PHASE

CALIBRATION

-19.2µs to +19.2µs

±0.69 @ 50Hz, 0.022

±0.83 @ 60Hz, 0.024

0.1

50Hz

00011

VA delayed by 4.8µs

(-0.086 @ 50Hz)

1Ch

Figure 17 – Phase Calibration

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