Data Sheet

ADL5506

Rev. A | Page 21 of 23

= open. Placing capacitance from CFLT to VLOG decreases the

noise spectral density and the integrated noise. The choice of

integrated noise and noise spectral density at a given frequency.

the output, and thus controls the output response time to an RF

pulse (see the VLOG Pulse Response Time section).

capacitance on the CFLT node is the internal capacitor. Adding

off-chip capacitance from the CFLT pin to the VLOG pin decreases

the video bandwidth and slows the output response to an RF

input pulse. See the Filter Capacitor section for an approximate

Figure 28 shows the response time when the ENBL pin is pulsed

while having the VPOS pin connect to a 3.0 V supply and an RF

signal applied at RFIN. The sharp pulse that is seen on VLOG

preceding the actual response of the detectors, which happens

approximately 0.5 µs later, is the power-up transient that occurs

in the output stage. The upper voltage limit of these power-up

transients is 2.25 V typical, for a 3.0 V supply. Ensure that these

power-up transients do not overload the circuit that the VLOG

pin drives.

Device Handling

The wafer level chip scale package consists of solder bumps

connected to the active side of the die. The device is lead-free with

95.5% tin, 4.0% silver, and 0.5% copper solder bump composition.

The WLCSP package can be mounted on printed circuit boards

using standard surface-mount assembly techniques; however,

take caution to avoid damaging the die. See the AN-617

Application Note for additional information. WLCSP devices

are bumped die, and exposed die can be sensitive to light

conditions, which can influence specified limits.