ADL5506

Data Sheet

Rev. A | Page 22 of 23

EVALUATION BOARD

Figure 51 shows the schematic of the ADL5506 evaluation board.

The board is powered by a single supply in the 2.5 V to 5.5 V range.

The power supply is decoupled by 100 pF and 0.1 μF capacitors.

Enable the device by switching SW1 to the on position.

The RF input has a broadband match of 50 Ω using a single

52.3 Ω resistor at R7. More precise matching at spot frequencies

is possible (see the Input Coupling Options section).

Table 6 details the various configuration options of the evaluation

board. Figure 52 shows the layout of the evaluation board.

LAND PATTERN AND SOLDERING INFORMATION

Pad diameters of 0.20 mm are recommended with a solder

mask opening of 0.30 mm. For the RF input trace, a trace width

of 0.30 mm is used, which corresponds to a 50 Ω characteristic

impedance for the dielectric material being used (FR4). All traces

going to the pads are tapered down to 0.15 mm. For the RFIN

line, the length of the tapered section is 0.20 mm.

Figure 51. Evaluation Board Schematic

Figure 52. Layout of Evaluation Board, Component Side

Table 6. Evaluation Board Configuration Options

Component

Description

Default Condition

VPOS, GND

Ground and supply vector pins.

Not applicable

C1, C2, C5, C6,

C7, C8, C9

Power supply decoupling. Nominal supply decoupling of 0.1 μF and 100 pF.

C1, C6 = 100 pF (Size 0402),

C2, C5, C9 = 0.1 μF (Size 0402),

C7 = C8 = open (Size 0805)

R7

RF input interface. The 52.3 Ω resistor at R7 combines with the ADL5506 internal input

impedance to give a broadband input impedance of around 50 Ω.

R7 = 52.3 Ω (Size 0402)

C3, C4, R2, R3

Output filtering. The combination of the internal 100 Ω output resistance and C4 produce

a low-pass filter to reduce the output ripple of the VLOG output. The output can be

scaled down using the resistor divider pads, R2 and R3.

R3 = 0 Ω (Size 0402),

R2 = open (Size 0402),

C3, C4 = open (Size 0402)

SW1, R4, R10, P2

Device enable. When SW1 is set to the on position, the ENBL pin is connected to the

supply and the ADL5506 is in enable mode. When SW1 I set to the off position, the ENBL

pin is grounded (through the 0 Ω resistor), putting the device in power-down mode.

R4 = 0 Ω (Size 0402),

R10 = open (Size 0402),

SW1= on position,

P2 = not installed

P1, R1, R5, R6,

R8, R9

Alternate interface. The end connector, P1, allows access to various ADL5506 signals.

These signal paths are only used during factory test and characterization.

P1 = not installed,

R1, R5, R6, R9 = open (Size 0402),

R8 = open (Size 0805)

ADL5506

C8

(OPEN)

VPOS

VLOG

ENBL

1

VLOG

COMM

2

3

CFLT

6

VPOS

5

RFIN

4

C7

(OPEN)

RFIN

(P1 – B6)

(P1 – B8)

(P1 – B12)

(P1 – A1, B1)

(P1 – B4)

EN

R5

(OPEN)

R3

0Ω

R2

(OPEN)

R9

(OPEN)

C4

(OPEN)

C1

100pF

C2

0.1µF

C9

0.1µF

VP

C5

0.1µF

C6

100pF

C3

(OPEN)

R7

52.3Ω

R6

(OPEN)

R1

(OPEN)

VP

VP

SW1

R8

(OPEN)

R10

(OPEN)

P2

R4

0Ω