DocID027248 Rev 2

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L2G2IS

Register description

26

7.7

CTRL_REG2 (0Ch)

7.8

CTRL_REG3 (0Dh)

Table 19. Operating mode selection

PW1

PW0

Operating mode selection

0

0

Power-down

0

1

Power-down

1

0

Sleep mode

1

1

Normal mode

Table 20. CTRL_REG2 register

LPF_O

1. These bits must be set to ‘0’ for proper operation of the device.

HPreset

SWreset

HPF

Table 21. CTRL_REG2 description

LPF_O

Low-pass filter order selection. Default value: 0

(0: 2nd order; 1: 1st order).

Refer to Figure 9: LPF chain block diagram and Table 24: Low-pass filter cutoff fre-

quency selection

HPreset

High-pass filter reset. Default value: 0

(1: HPF reset on X and Y-axis)

SWreset

Software reset. Default value: 0

(1: all the configuration register values are restored to default values).

HPF

High-pass filter enable. Default value: 0

(0: high-pass filter is disabled; 1: high-pass filter is enabled)

Table 22. CTRL_REG3 register

1. These bits must be set to ‘0’ for proper operation of the device.

ST

PP_OD

DRDY _EN

LPF_D

Table 23. CTRL_REG3 description

ST

Self-test enable. Default value: 0

(0: Self-test disabled; 1: Self-test enabled)

PP_OD

DRDY pin configuration. Default value: 0

(0: push-pull; 1: open drain)

DRDY_EN

Data ready enable on DRDY pin. Default: 0

(1: DRDY on pin). Section 2.3: Data-ready interrupt and synchronous reading.

LPF_D

Digital low-pass filter enable. Default value: 0

(0: digital low-pass filter disabled; 1: digital low-pass filter enabled).

Refer to Figure 9: LPF chain block diagram and Table 24: Low-pass filter cutoff

frequency selection.