LSM330D datasheet(21/66 Pages) STMICROELECTRONICS

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LSM330D

Functionality

Doc ID 022562 Rev 2

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4.1.3

6D/4D orientation detection

The LSM330D includes 6D/4D orientation detection. In this configuration the interrupt is

generated when the device is stable in a known direction. In 4D configuration, Z axis

position detection is disabled.

4.1.4

“Sleep-to-wake” and “Return to sleep”

The LSM330D can be programmed to automatically switch to Low power mode upon

recognition of a determined event. Once the event condition is over, the device returns to the

preset Normal mode.

To enable this function, the desired threshold value must be stored in the Act_THS register,

while the duration value is written in the Act_DUR register.

When the internally high-pass filtered acceleration becomes lower than the threshold value

on all the three axes, the device automatically switches to Low power mode (10Hz ODR).

During this condition, the ODRx bits and LPen bit in the CTRL_REG1_G register and the

HR bit in the CTRL_REG3_G register are not considered.

When the acceleration goes back over the threshold (on at least one axis), the system

restores the operating mode and ODRs as per the CTRL_REG1_G register and

CTRL_REG3_G register settings.

Accelerometer digital main blocks

4.1.5

FIFO

The LSM330D embeds 32 slots of data FIFO for each of the three output channels: X, Y and

Z. This allows consistent power saving for the system, since the host processor does not

need to continuously poll data from the sensor, but it can wake up only when needed and

burst the significant data out from the FIFO. This buffer can work accordingly in four different

modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is

selected by the FIFO_MODE bits in the FIFO_CTRL_REG_A register. Programmable

watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated

interrupts on the INT1_A/INT2_A pin (configured through the FIFO_CTRL_REG_A

4.1.6

Bypass mode

In Bypass mode, the FIFO is not operational and for this reason it remains empty. For each

channel only the first address is used. The remaining FIFO slots are empty.

4.1.7

FIFO mode

In FIFO mode, data from the X, Y and Z channels are stored into the FIFO. A watermark

interrupt can be enabled (FIFO_WTMK_EN bit in the FIFO_CTRL_REG_A register in order

to be raised when the FIFO is filled to the level specified into the FIFO_WTMK_LEVEL bits

of the FIFO_CTRL_REG_A register. The FIFO continues filling until it is full (32 slots of data

for X, Y and Z). When full, the FIFO stops collecting data from the input channels.

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