PC87570 datasheet(17/168 Pages) NSC

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Introduction

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1.3.2

IRD Environment

IRD environment is used mostly for prototypes and low-vol-

ume manufacturing. In this environment, the on-chip Base

Memory (containing the up to 2 KByte boot code), is re-

placed by up to 64 Kbytes of off-chip memory, called off-

chip Base Memory, which may be ROM or Flash memory.

You can control the number of wait states used to access the

Base Memory to allow interfacing with devices that have a

wide range of access times. Configure this number according

to the operation frequency and voltage, and the device ac-

cess time. Since the time required to access off-chip Base

Memory devices affects the performance of the CR16A core,

use the same number of wait states in all environments to

maintain cycle-by-cycle compatibility.

In this environment, the pins of ports PF and PG are allocat-

ed for the interface to the Base Memory. The system may

restore these ports using the I/O Expansion protocol and

off-chip logic, while maintaining cycle-by-cycle and binary

compatibility with the IRE environment. All features of IRE

environment can be implemented either directly or by using

additional external logic.

Figure 1-2 illustrates a system in IRD environment.

Clock

External

Memory

PC87570

32KX1/32KCLKIN

32KX2

HMR

HA18-0

HD7-0

HIOR

HIOW

IRQ1

IRQ11

IRQ12

WR1-0

SEL0

A18-16, A15-0

D15-8

AD7-0

DA3-0

PA6-0

PB7-0

PC7-0

PD7-0

HIOCHRDY

RTC

Battery

VBAT

IRQ8

Crystal

32.768 KHz

External Keyboard

Internal

Keyboard

KBSOUT15-0

KBSIN7-0

SRAM or

Flash

ENV0

GA20

AVCC

AGND

VCC

GND

Power

Supply

SCL

D7-0

HMEMRD

HMEMWR

PG4-0

PE1-0

PF7-0

PH5-0

HMEMCS

HAEN

EXINT0,10,11,15

PFAIL

RING

SHBM

HRMS

Conﬁguration

Inputs

I/O

Expansion

HDEN

TRIS

HPWRON

PC0

External Mouse

Auxiliary PS/2

Interface

HRSTO

SELIO

(Matrix)

SDA

SWIN

Analog

Reset

Control

(power-up reset)

GPIO

Interrupt

ACCESS.bus

System

Timers

ENV1

Figure 1-2. IRD Environment

SEL1

(Application)

VREF

ADC

DAC

Off-chip

Base

(Boot code

ROM)

Memory

Restored

Ports

* Optional 8/16 data bus

VCC

PC87570 数据表(PDF) 17 Page - National Semiconductor (TI)

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