PC87570 datasheet(21/168 Pages) NSC

21 / 168 page

Signal/Pin Connection and Description

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2.2

SIGNAL/PIN DESCRIPTIONS

Refer to Table 2-2 for an alphabetical listing of all PC87570 signals and pins, as well as brief descriptions. The following

abbreviations are used in the Type column in this table.

Table 2-1. Type Symbols

Table 2-2. PC87570 Signals

Symbol

Description

DC Characteristics

TTL

Input, TTL compatible

See Table 19-7 on page 135.

CMOSS

Input, CMOS with Schmidt Trigger

See Table 19-7 on page 135.

STRAP

Input with Schmidt characteristics and an internal

pull-down resistor, typically used for strap signals

See Table 19-7 on page 135.

Output, CMOS buffer

See Table 19-7 on page 135.

CMHD1

Output, CMOS buffer with high drive type 1

See Table 19-7 on page 135.

CMHD2

Output, CMOS buffer with high drive type 2

See Table 19-7 on page 135.

Output, Open-Drain

See Table 19-7 on page 135.

OD2

Output, Open-Drain with high drive type 2

See Table 19-7 on page 135.

Weak pull-up capability (on input or output pin)

See Table 19-7 on page 135.

OSCIN

Oscillator input [not characterized]

OSCOUT

Oscillator output [not characterized]

ANIN

Analog input signal

See Table 19-5 on page 134.

ANOUT

Analog output signal

See Table 19-6 on page 134.

Signal

Pin Number

Buffer Type

Function

160-pin

176-pin

Input

Output

32KCLKIN

TTL

32.768 KHz Oscillator Clock Input..

32KX1

OSCIN

32.768 KHz Crystal Interface, input to oscillator.

32KX2

OSCOUT

32.768 KHz Crystal Oscillator Interface output

to crystal. See Figure 6-1 on page 65.

A18-0

122-104

136, 135,

130-114

Address A18 through A0. CR16A address to

external memory. A16-A17 should not be pulled

up during power-up since include special test

features.

AD7-0

84, 83,

80-75

95, 94,

86-81

ANIN

Analog Inputs of the A/D converter

AGND

N/A

Analog Ground, for ADC and DAC.

AVCC

N/A

Analog 5V or 3.3V power supply.

BE1,0

118, 117

128, 127

Byte Enable bits 1 and 0 on monitor bus cycles.

BST2-0

92-94

102-104

Bus Status bits 2-0 on monitor bus cycles.

When in DEV environment, these pins allows

monitoring of the external bus cycles. When

BCFG.OBR is also set, the internal bus cycles

are also visible outside. See also Table 2-5 on

page 27.

CBRD

119

129

Core Bus Read Status on monitor bus cycles.

Available in all modes. See Table 2-5 on

page 27.

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