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数据搜索系统，热门电子元器件搜索 |
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L99MD02 数据表(PDF) 24 Page - STMicroelectronics |
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L99MD02 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 46 page  Functional description of the SPI L99MD02 24/46 Doc ID 16082 Rev 5 Figure 8. SPI frame structure 6.2 SPI communication flow 6.2.1 General description The proposed SPI communication is based on a standard SPI interface structure using CSN (Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock) signal lines. Maximum SPI frequency is 1 MHz. At the beginning of each communication the master reads the <SPI-frame-ID> register (ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length (24 bit for the L99MD02) and the availability of additional features. Each communication frame consists of an instruction byte which is followed by 2 data bytes (Figure 8). |
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