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TNETV2664FIDZWT 数据表(PDF) 44 Page - Texas Instruments |
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TNETV2664FIDZWT 数据表(HTML) 44 Page - Texas Instruments |
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44 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION ZWT ZDU NAME NO. NO. PCI EM_A[16]/PGNT/ IPD This pin is multiplexed between the EMIFA, PCI, and GPIO. C11 B13 I/O/Z GP[48] DVDD33 In PCI mode, this pin is PCI bus grant (I) EM_A[18]/PRST/ IPD THIS pin is multiplexed between the EMIFA, PCI, and GPIO. D11 A14 I/O/Z GP[46] DVDD33 In PCI mode, this pin is PCI reset (I) EM_A[19]/PREQ/ IPD This pin is multiplexed between the EMIFA, PCI, and GPIO. B12 C14 I/O/Z GP[45] DVDD33 In PCI mode, this pin is the PCI bus request (O/Z) EM_A[20]/PINTA/ IPD This pin is multiplexed between the EMIFA, PCI, and GPIO. C12 C15 I/O/Z GP[44] DVDD33 In PCI mode, this pin is the PCI interrupt A (O/Z) EM_A[12]/PCBE3/ IPD This pin is multiplexed between EMIFA, PCI, and GPIO. D10 B12 I/O/Z GP[89] DVDD33 In PCI mode, this pin is the PCI command/byte enable 3 (I/O/Z). HD3/VLYNQ_RXD2/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. B7 B8 I/O/Z PCBE2 /GP[61] DVDD33 In PCI mode, this pin is the PCI command/byte enable 2 (I/O/Z) HD11/MTXD3/ IPD This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO. C5 A5 I/O/Z PCBE1/GP[69] DVDD33 In PCI mode, this pin is the PCI command/byte enable 1 (I/O/Z) HRDY/MRXD2/ IPU This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO. D2 C3 I/O/Z PCBE0/GP[80] DVDD33 In PCI mode, this pin is the PCI command/byte enable 0 (I/O/Z) EM_A[9]/PIDSEL/ IPD This pin is multiplexed between EMIFA, PCI, and GPIO. D9 C11 I/O/Z GP[92] DVDD33 In PCI mode, this pin is the PCI initialization device select (I) VLYNQ_CLOCK/ IPU This pin is multiplexed between VLYNQ, PCI, and GPIO. A7 A8 I/O/Z PCICLK/GP[57] DVDD33 In PCI mode, this pin is the PCI clock (I) HD4/VLYNQ_RXD3/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. C7 C8 I/O/Z PFRAME/GP[62] DVDD33 In PCI mode, this pin is the PCI frame (I/O/Z) HD5/VLYNQ_TXD0/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. A6 A7 I/O/Z PIRDY/GP[63] DVDD33 In PCI mode, this pin is the PCI initiator ready (I/O/Z) HD6/VLYNQ_TXD1/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. D6 C7 I/O/Z PTRDY/GP[64] DVDD33 In PCI mode, this pin is the PCI target ready (I/O/Z) HD7/VLYNQ_TXD2/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. B6 B7 I/O/Z PDEVSEL/GP[65] DVDD33 In PCI mode, this pin is the PCI device select (I/O/Z) HD8/VLYNQ_TXD3/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. A5 A6 I/O/Z PPERR/GP[66] DVDD33 In PCI mode, this pin is the PCI parity error (I/O/Z) HD9/MCOL/ IPD This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO. C6 C6 I/O/Z PSTOP/GP[67] DVDD33 In PCI mode, this pin is the PCI stop (I/O/Z) HD10/MCRS/ IPD This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO. B5 B6 I/O/Z PSERR/GP[68] DVDD33 In PCI mode, this pin is the PCI system error (I/O/Z) HD12/MTXD2/ IPD This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO. D5 C5 I/O/Z PPAR/GP[70] DVDD33 In PCI mode, this pin is the PCI parity (I/O/Z) (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors. (3) Specifies the operating I/O supply voltage for each signal 44 Device Overview Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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