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TNETV2664FIDZWT 数据表(PDF) 49 Page - Texas Instruments |
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TNETV2664FIDZWT 数据表(HTML) 49 Page - Texas Instruments |
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49 / 249 page ![]() TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 2-17. VLYNQ Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION ZWT ZDU NAME NO. NO. VLYNQ VLYNQ_CLOCK/ IPU This pin is multiplexed between VLYNQ, PCI, and GPIO. A7 A8 I/O/Z PCICLK/GP[57] DVDD33 For VLYNQ, it is the clock VLYNQ_CLOCK [I/O/Z]. This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. HD0/VLYNQ_SCRUN/ IPU C8 B9 I/O/Z For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN AD18/GP[58] DVDD33 [I/O/Z]. HD8/VLYNQ_TXD3/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. A5 A6 I/O/Z PPERR/GP[66] DVDD33 For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3. HD7/VLYNQ_TXD2/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. B6 B7 I/O/Z PDEVSEL/GP[65] DVDD33 For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2. HD6/VLYNQ_TXD1/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. D6 C7 I/O/Z PTRDY/GP[64] DVDD33 For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1. HD5/VLYNQ_TXD0/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. A6 A7 I/O/Z PIRDY/GP[63] DVDD33 For VLYNQ, it is transmit bus bit 0 output VLYNQ_TXD0. HD4/VLYNQ_RXD3/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. C7 C8 I/O/Z PFRAME/GP[62] DVDD33 For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3. HD3/VLYNQ_RXD2/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. B7 B8 I/O/Z PCBE2/GP[61] DVDD33 For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2. HD2/VLYNQ_RXD1/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. A8 A9 I/O/Z AD17/GP[60] DVDD33 For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1. HD1/VLYNQ_RXD0/ IPD This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO. D7 C9 I/O/Z AD16/GP[59] DVDD33 For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0. (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors. (3) Specifies the operating I/O supply voltage for each signal Copyright © 2007–2009, Texas Instruments Incorporated Device Overview 49 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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