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TNETV2664FIDZWT 数据表(PDF) 69 Page - Texas Instruments |
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TNETV2664FIDZWT 数据表(HTML) 69 Page - Texas Instruments |
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69 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 3-2. VDD3P3V_PWDN Register Bit Descriptions (1) (continued) BIT NAME DESCRIPTION Timer0 Block I/O Power Down Control. Controls the power of the 2 I/O pins in the Timer0 Block. 8 TIMER0 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. Serial Port Block I/O Power Down Control. Controls the power of the 12 I/O pins in the Serial Port Block (Serial Port Sub-Block 0 and Serial Port Sub-Block 1). 7 SP 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. PWM1 Block I/O Power Down Control. Controls the power of the 1 I/O pin in the PWM1 Block. 6 PWM1 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. GPIO Block I/O Power Down Control. Controls the power of the 4 I/O pins in the GPIO Block. 5 GPIO 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). Host Block I/O Power Down Control. Controls the power of the 27 I/O pins in the Host Block. 4 HOST 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA Sub-Block 2 I/O Power Down Control. Controls the power of the 3 I/O pins in the EMIFA Sub-Block 2. 3 EMBK2 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA Sub-Block 1 I/O Power Down Control. Controls the power of the 29 I/O pins in the EMIFA Sub-Block 1. 2 EMBK1 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA Sub-Block 0 I/O Power Down Control. Controls the power of the 21 I/O pins in the EMIFA Sub-Block 0. 1 EMBK0 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). CLKOUT Block I/O Power Down Control. Controls the power of the 1 I/O pin in the CLKOUT Block. 0 CLKOUT 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). 3.3 Clock Considerations Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and the Power and Sleep Controller (PSC). 3.3.1 Clock Configurations after Device Reset After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). Copyright © 2007–2009, Texas Instruments Incorporated Device Configurations 69 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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