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TNETV2666FIBZWT 数据表(PDF) 188 Page - Texas Instruments |
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TNETV2666FIBZWT 数据表(HTML) 188 Page - Texas Instruments |
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188 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com 6.12 Host-Port Interface (HPI) Peripheral 6.12.1 HPI Device-Specific Information The C6424 device includes a user-configurable 16-bit Host-port interface (HPI16). Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the C6424. 6.12.2 HPI Peripheral Register Description(s) Table 6-35. HPI Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01C6 7800 PID Peripheral Identification Register The CPU has read/write 01C6 7804 PWREMU_MGMT HPI power and emulation management register access to the PWREMU_MGMT register. 01C6 7808 - 01C6 7824 - Reserved 01C6 7828 - Reserved 01C6 782C - Reserved The Host and the CPU both 01C6 7830 HPIC HPI control register have read/write access to the HPIC register. HPIA HPI address register The Host has read/write 01C6 7834 (HPIAW)(1) (Write) access to the HPIA registers. The CPU has only read HPIA HPI address register 01C6 7838 access to the HPIA registers. (HPIAR)(1) (Read) 01C6 783C - 01C6 7FFF - Reserved (1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the Host. The CPU can access HPIAW and HPIAR independently. For more details about the HPIA registers and their modes, see the TMS320C642x DSP Host Port Interface (HPI) User's Guide (literature number SPRUEM9). 188 Peripheral Information and Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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