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TNETV2666FIBZWT 数据表(PDF) 186 Page - Texas Instruments

部件名 TNETV2666FIBZWT
功能描述  Fixed-Point Digital Signal Processor
PDF  249 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2666FIBZWT 数据表(HTML) 186 Page - Texas Instruments

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10
8
4
3
7
12
5
6
14
2
3
13
Stop
Start
Repeated
Start
Stop
SDA
SCL
1
11
9
TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
www.ti.com
Figure 6-21. I2C Receive Timings
Table 6-34. Switching Characteristics for I2C Timings(1) (see Figure 6-22)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
PARAMETER
STANDARD
UNIT
FAST MODE
MODE
MIN
MAX
MIN
MAX
16
tc(SCL)
Cycle time, SCL
10
2.5
µs
Delay time, SCL high to SDA low (for a repeated START
17
td(SCLH-SDAL)
4.7
0.6
µs
condition)
Delay time, SDA low to SCL low (for a START and a repeated
18
td(SDAL-SCLL)
4
0.6
µs
START condition)
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
td(SDAV-SCLH)
Delay time, SDA valid to SCL high
250
100
ns
22
tv(SCLL-SDAV)
Valid time, SDA valid after SCL low
0
0
0.9
µs
Pulse duration, SDA high between STOP and START
23
tw(SDAH)
4.7
1.3
µs
conditions
20 + 0.1Cb
24
tr(SDA)
Rise time, SDA
1000
300
ns
(1)
20 + 0.1Cb
25
tr(SCL)
Rise time, SCL
1000
300
ns
(1)
20 + 0.1Cb
26
tf(SDA)
Fall time, SDA
300
300
ns
(1)
20 + 0.1Cb
27
tf(SCL)
Fall time, SCL
300
300
ns
(1)
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
4
0.6
µs
29
Cp
Capacitance for each I2C pin
10
10
pF
(1)
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
186
Peripheral Information and Electrical Specifications
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320C6424



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