STLED325 datasheet(13/62 Pages) STMICROELECTRONICS

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STLED325

Functional description

Doc ID 17576 Rev 1

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3.6.2

Watchdog timer

Another watchdog timer is present in the Watchdog timer register at address 09h of the RTC

Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution

where:

000 = 1/16 second (16 Hz);

001 = 1/4 second (4 Hz);

010 = 1 second (1 Hz);

011 = 4 seconds (1/4 Hz); and

100 = 1 minute (1/60 Hz).

The Watchdog timer is programmed by setting the desired timeout into the Watchdog

the 5-bit multiplier value with the resolution values depicted by the watchdog resolution bits.

The Watchdog timer is disabled when its register is cleared by writing a value of 00h.

Hence the Watchdog function is not enabled upon power on. It is enabled when a non-zero

value is written into its register. The Watchdog timer is reset by performing a write to the

watchdog register, then the time-out period starts over.

If the processor does not reset the timer within the specified timeout period, and when the

timeout occurs, the watchdog flag is set. The watchdog timer of RTC is cleared by writing a

00 value and starts again whenever any new value is written to it.

The WatchDogEn Flag can be disabled or enabled by writing to the register bit and the reset

of watchdog timer is done by writing to the register.

3.7

Power-on-reset and soft-start

The device integrates two internal power-on-reset circuits which initialize the digital logic

upon power up. One circuit is for the VCC power and the other is for the VBAT power. The

soft-start circuit limits the inrush current and high peak current during power-up. This is done

by delaying the input circuit’s response to the external applied voltage. During soft-start, the

input resistance is higher which lowers the in-rush current when the supply voltage is

applied.

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