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TNETV2685FIBZUT5 数据表(PDF) 46 Page - Texas Instruments |
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TNETV2685FIBZUT5 数据表(HTML) 46 Page - Texas Instruments |
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46 / 191 page  TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com Table 3-7. PINMUX Register Field Descriptions (continued) Bit Field Value Description 9:8 MCASP_EN Controls the pin muxing between McASP and VIC UNMUXED MUXED (11) STCLK, VCTL, or McASP 00 3-state 01 McASP (all McASP Pins) 10 (McASP without AXR8, AXR9) ACLKR AFSR AXR0 AXR1 AC:LKX AFSX AXR2 AXR3 AHCLKR AMUTEIN AXR4 AXR5 AHCLKX AMUTE AXR6 AXR7 STCLK VCTL 11 Reserved 7:6 Reserved Reserved 5:4 VLYNQ_EN Controls the pin muxing between Video Port 2 and VLYNQ UNMUXED(12) MUXED(13) VP2#1 VP2#2 VLYNQ 00 3-state 3-state 01 3-state 3-state 10 Enable VP2D12-19, VP2CLK1, VP2CTL2 11 Enable VRXD0-3 and VTXD0-3, VCLK, VSCRUN 3:1 Reserved Reserved 0 TIMER_EN Controls the pin muxing between TIMER and GPIO[8:11] MUXED(14) 0 GPIO[8:11] 1 Timer 0/1 (11) The complete list of pins: AC4, AC3, AC6, AC7, W6, AA7, AB6, Y6, AA6, AB4, Y5, V7, AA4, V6, Y7, AA5, AB3, U7 (12) For the first half of the Video Port 2, the complete list of pins with function: AB1(VP2CLK0), AA1 (VP2CTL0), AB2 (VP2CTL1) and W5, AA2, Y3, U6, Y2, W3, V5, W4 (VP2D02, VP2D03, VP2D04, VP2D05, VP2D06, VP2D07, VP2D08, VP2D09) (13) For the second half of the Video Port 2, the complete list of pins with function: W1 (VP2CLK1/VCLK), Y1(VP2CTL2/VSCRUN), W2, V3, V4, U1, U3, U2, U5, U4 (VP2D12/VRXD0, VP2D13/VRXD1, VP2D14/VRXD2, VP2D15/VRXD3, VP2D16/VTXD0, VP2D17/VTXD1, VP2D18/VTXD2, VP2D19/VTXD3) (14) The complete list of pins:E20, D21, E21, C22 46 Device Configuration Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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