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TNETV2685FIBZUT5 数据表(PDF) 87 Page - Texas Instruments |
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TNETV2685FIBZUT5 数据表(HTML) 87 Page - Texas Instruments |
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87 / 191 page  TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 6.7.7 Reset Controller Register The reset type status (RSTYPE) register is the only register for the reset controller. The RSTYPE register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The reset type status register is shown in Figure 6-9 and described in Table 6-22. Figure 6-9. Reset Type Status Register (RSTYPE) 31 16 Reserved R-0 15 4 3 2 1 0 Reserved SRST MRST WRST POR R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-22. Reset Type Status Register (RSTYPE) Field Descriptions Bit Field Value Description 31:4 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. 3 SRST System reset 0 System Reset was not the last reset to occur. 1 System Reset was the last reset to occur. 2 MRST Max reset 0 Max Reset was not the last reset to occur. 1 Max Reset was the last reset to occur. 1 WRST Warm reset 0 Warm Reset was not the last reset to occur. 1 Warm Reset was the last reset to occur. 0 POR Power-on reset 0 Power-on Reset was not the last reset to occur. 1 Power-on Reset was the last reset to occur. 6.7.8 Pin Behaviors at Reset During normal operation, devices pins are controlled by the selected peripheral. During device level global reset, the pin behaviors are classified into the following Reset Groups: • Z Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins remain 3-stated until configured otherwise by their respective peripheral (after the peripheral is enabled by the PSC). • Z/High Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins drive a logic High. • Z/Low Group: These pins are 3-stated when a device-level global reset source (e.g. POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins drive a logic Low. • DDR2 Z/High Group: These pins are 3-stated when a device-level global reset source (e.g. POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven High. • DDR2 Low/High Group: These pins are driven Low when a device-level global reset source (e.g. POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven High. • DDR2 High/Low Group: These pins are driven High when a device-level global reset source (e.g. POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven Low. Copyright © 2007–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 87 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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