TNETV2685FIDZUT7 datasheet(65/191 Pages) TI1

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DIVIDER D4

CLKIN1

PLLEN (PLLCTL.[0])

SYSCLK1

SYSCLK2

AECLKIN (External EMIF Clock Input)

EMIFA

DIVIDER PREDIV

DIVIDER D1

DIVIDER D2

AECLKOUT

PLLV1

EMI Filter

+1.8 V

560 pF

SYSCLK5

SYSREFCLK

(C64x+ MegaModule)

DIVIDER D5

PLL1 Controller

(EMIF Input Clock)

/1, /2, /3

ENA

PREDEN (PREDIV.[15])

ENA

/4 ... /8

PLL1

D4EN (PLLDIV4.[15])

SYSCLK4

(Internal

EMIF Clock

Input)

SYSCLK5

SYSCLK3

DIVIDER D3

SYSCLK6

DIVIDER D6

ENA

D2EN (PLLDIV2.[15])

/1, /2,

..., /8

(Emulation and Trace)

VICP cop_clk/2

VICP cop_clk

0 1

AECLKINSEL

(AEA[17] pin)

0 1

VCLK

VLYNQ

CLKDIR

(CTRL.[15])

/1, /2,

..., /8

CLKDIV

(CTRL.[18:16])

PLLM

x1,

x16 to x32

0.1 F

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.4

PLL1 Controller

The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as

well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the

external memory interface (EMIFA). Figure 6-5 shows a functional block diagram of the PLL Input Clock.

Figure 6-5. PLL Input Clock

Peripheral Information and Electrical Specifications

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TNETV2685FIDZUT7 数据表(PDF) 65 Page - Texas Instruments

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