DocID025723 Rev 4

21/29

ST1S50

Application information

29

c)

Quiescent current losses, calculated as:

Equation 29

Equation 30

as the parallel of many paths of heat conduction from the junction to the ambient. For this

device the path through the exposed pad is the one conducting the largest amount of heat.

for the VFDFPN10 package.

Figure 10. Switching losses

6.7

Layout consideration

The PC board layout of the switching DC/DC regulator is very important to minimize the

noise injected in high impedance nodes, to reduce interferences generated by the high

switching current loops and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops have to be as short as

possible. In the buck converter two are the high switching current loops: during the ON-time,

the pulsed current flows through the input capacitor, the high-side power switch, the inductor

and the output capacitor; during the OFF-time, through the low-side power switch, the

inductor and the output capacitor.

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=

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+

=