L6706 datasheet(41/47 Pages) STMICROELECTRONICS

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L6706

System control loop compensation

Doc ID 15698 Rev 2

41/47

desired crossover frequency

T. Neglecting the effect of ZF(s), the transfer function has one

zero and two poles; both the poles are fixed once the output filter is designed (LC filter

resonance

LC) and the zero (ωESR) is fixed by ESR and the droop resistance.

Figure 24.

Equivalent control loop block diagram (left) and bode diagram (right)

To obtain the desired shape an RF - CF series network is considered for the ZF(s)

implementation. A zero at

F = 1/RFCF is then introduced together with an integrator. This

integrator minimizes the static error while placing the zero

F in correspondence with the L-

C resonance assures a simple -20 dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at

frequency lower than the above reported zero.

Compensation network can be simply designed placing

F = ωLC and imposing the cross-

over frequency

T as desired obtaining (always considering that ωT might be not higher than

1/10th of the switching frequency FSW):

Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a

capacitor between COMP pin and FB pin (it does not change the system bandwidth):

VREF

COMP

VSEN

FBG

RFB

PWM

ESR

d VOUT

VOUT

ZF(s)

ZFB(s)

ZF(s)

GLOOP(s)

LC = ωF

ESR

RF[dB]

ΔV

OSC

⋅

----------------------------------

---

DROOP

ESR

()

-----------------------------------------------

⋅⋅

⋅

--------------------

π R

⋅

⋅⋅

---------------------------------------

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