L6706 datasheet(43/47 Pages) STMICROELECTRONICS

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L6706

Layout guidelines

Doc ID 15698 Rev 2

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Layout guidelines

Since the device manages control functions and high-current drivers, layout is one of the

most important things to consider when designing such high current applications. A good

layout solution can generate a benefit in lowering power dissipation on the power paths,

reducing radiation and a proper connection between signal and power ground can optimize

the performance of the control loops. Two kind of critical components and connections have

to be considered when layouting a VRM based on L6706: power components and

connections and small signal components connections.

20.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components has to be

reserved to this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be a part of a power plane and anyway realized by wide and thick copper traces: loop

must be anyway minimized. The critical components, i.e. the power transistors, must be

close one to the other. The use of multi-layer printed circuit board is recommended.

Figure 26 shows the details of the power connections involved and the current loops. The

input capacitance (CIN), or at least a portion of the total capacitance needed, has to be

placed close to the power section in order to eliminate the stray inductance generated by the

copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be

connected near the HS drain. Use proper VIAs number when power traces have to move

between different planes on the PCB in order to reduce both parasitic resistance and

inductance. Moreover, reproducing the same high-current trace on more than one PCB layer

will reduce the parasitic resistance associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic

inductance and resistance associated to the copper trace also adding extra decoupling

capacitors along the way to the load when this results in being far from the bulk capacitor

bank.

Gate traces must be sized according to the driver RMS current delivered to the power

MOSFET. The device robustness allows managing applications with the power section far

from the controller without losing performances. External gate resistors help the device to

dissipate power resulting in a general cooling of the device. When driving multiple

MOSFETs in parallel, it is suggested to use one resistor for each MOSFET.

20.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply (see Figure 26). Locate the bypass capacitor

(VCC and bootstrap capacitor) close to the device and refer sensible components such as

frequency set-up resistor ROSC, over current resistor ROCSET. Star grounding is suggested:

connect SGND to PGND plane in a single point to avoid that drops due to the high current

delivered causes errors in the device behavior.

Remote sensing connection must be routed as parallel nets from the FBG/VSEN pins to the

load in order to avoid the pick-up of any common mode noise. Connecting these pins in

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