ST7MC1K2 datasheet(69/371 Pages) STMICROELECTRONICS

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Interrupts

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7.8

Nested interrupts register map and reset values

2:1 IS3[1:0]

Interrupt sensitivity (ei0 sensitivity)

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following

external interrupts:

External interrupt ei0 (port D[6:4]):

00: External interrupt sensitivity = falling edge and low level (IPA bit = 0)

and rising edge and high level (IPA bit = 1)

01: External interrupt sensitivity = rising edge only (IPA bit = 0)

and falling edge only (IPA bit = 1)

10: external interrupt sensitivity = falling edge only (IPA bit = 0)

and rising edge only (IPA bit = 1)

11: external interrupt sensitivity = rising and falling edge (IPA bit = 0 and IPA bit = 1)

External interrupt ei0 (port D[3:1]):

00: External interrupt sensitivity = falling edge and low level

01: External interrupt sensitivity = rising edge only

10: External interrupt sensitivity = falling edge only

11: External interrupt sensitivity = rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1

(level 3).

0IPA

Interrupt polarity (for port D)

This bit is used to invert the sensitivity of port D [6:4] external interrupts. It can be set

and cleared by software only when I1 and I0 of the CC register are both set to 1

(level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Table 20.

EICR register description (continued)

Bit

Name

Function

Table 21.

Nested interrupts register map and reset values

Address (Hex.) Register label

0024h

ISPR0

Reset value

ei1

ei0

MCC + SI

MCES

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

0025h

ISPR1

Reset value

MTC C/D

MTC R/Z

MTC U/CL

ei2

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

0026h

ISPR2

Reset value

SCI

Timer B

Timer A

SPI

I1_11

I0_11

I1_10

I0_10

I1_9

I0_9

I1_8

I0_8

0027h

ISPR3

Reset value

PWMART

AVD

I1_15

I0_15

I1_14

I0_14

I1_13

I0_13

I1_12

I0_12

0028h

EICR

Reset value

IS11

IS10

IPB

IS21

IS20

IPA

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