ST7MC1K2 datasheet(78/371 Pages) STMICROELECTRONICS

78 / 371 page

Obsolete

Product(s)

- Obsolete

Product(s)

I/O ports

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

78/371

I/O ports

9.1

Introduction

The I/O ports offer different functional modes:

●

transfer of data through digital inputs and outputs and for specific pins,

●

external interrupt generation,

●

alternate signal input/output for the on-chip peripherals.

An I/O port contains up to eight pins. Each pin can be programmed independently as digital

input (with or without interrupt generation) or digital output.

9.2

Functional description

Each port has two main registers:

●

Data register (DR)

●

Data direction register (DDR)

and one optional register:

●

Option register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR

registers: Bit X corresponding to pin X of the port. The same correspondence is used for the

DR register.

The following description takes into account the OR register, (for specific ports which do not

provide this register refer to Section 9.3: I/O port implementation). The generic I/O block

diagram is shown in Figure 28.

9.2.1

Input modes

The input configuration is selected by clearing the corresponding DDR register bit. In this

case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Note:

Writing the DR register modifies the latch value but does not affect the pin status.

When switching from input to output mode, the DR register has to be written first to drive the

correct level on the pin as soon as the port is configured as an output.

Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this

might corrupt the DR content for I/Os configured as input.

External interrupt function

When an I/O is configured as input with interrupt, an event on this I/O can generate an

external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is

independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see Section 2:

Pin description and Section 7: Interrupts). If several input pins are selected simultaneously

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2 数据表(PDF) 78 Page - STMicroelectronics

ST7MC1K2 数据表(HTML) 78 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST7MC1K2 数据表(PDF) 78 Page - STMicroelectronics

ST7MC1K2 数据表(HTML) 78 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载