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ST7MC1K2 数据表(PDF) 234 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 234 Page - STMicroelectronics |
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234 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 234/371 10.6.8 PWM manager The PWM manager controls the motor via the six output channels in voltage mode or current mode depending on the V0C1 bit in the MCRA register. A block diagram of this part is given in Figure 107. Voltage mode In voltage mode (V0C1 bit = ‘0’), the PWM signal which is applied to the switches is generated by the 12-bit PWM generator compare U. Its duty cycle is programmed by software (refer to the PWM Generator section) as required by the application (speed regulation for example). The current comparator is used for safety purposes as a current limitation. For this feature, the detected current must be present on the MCCFI pin and the current limitation must be present on pin MCCREF. This current limitation is fixed by a voltage reference depending on the maximum current acceptable for the motor. This current limitation is generated with the VDD voltage by means of an external resistor divider but can also be adjusted with an external reference voltage ( ≤5V). The external components are adjusted by the user depending on the application needs. In voltage mode, it is mandatory to set a current limitation. As this limitation is set for safety purposes, an interrupt can be generated when the motor current feedback reaches the current limitation in voltage mode. This is the current limitation interrupt and it is enabled by setting the corresponding CLM bit in the MIMR register. This is useful in voltage mode for security purposes. The PWM signal is directed to the channel manager that connects it to the programmed outputs (see Figure 107). Over current handling in voltage mode When the current limitation interrupt is enabled by setting the CLIM bit in the MIMR register (available only in voltage mode), the OCV bit in MCRB register determines the effect of this interrupt on the MCOx outputs as shown in Table 101. For safety purposes, it can be necessary to put all MCOx outputs in reset state (high impedance, high state or low state depending on the setting made by the option byte) on a current limitation interrupt. This is the purpose of the OCV bit. When a current limitation interrupt occurs, if the OCV bit is reset, the effect on the MCOx outputs is only to put the PWM signal OFF on the concerned outputs. If the OCV bit is set, when the current limitation interrupt occurs, all the MCOx outputs are put in reset state. Table 101. OCV bit effect CLIM bit CLI bit OCV bit Output effect Interrupt 0 0 x Normal running mode No 0 1 x PWM is put OFF on current loop effect No 1 0 x Normal running mode No 1 1 0 PWM is put OFF on current loop effect Yes 1 1 1 All MCOx outputs are put in reset state (MOE reset)(1) 1. Only this functionality (CLIM = CLI = OCV = 1) is valid when the three PWM channels are enabled (PCN bit = 1 in the MDTG register). It can also be used as an over-current protection for three-phase PWM application (only if voltage mode is selected). Yes Obsolete Product(s) - Obsolete Product(s) |
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