ST72344S2 datasheet(71/247 Pages) STMICROELECTRONICS

71 / 247 page

ST72344xx, ST2345xx

Power-saving modes

Doc ID 12321 Rev 6

71/247

Figure 33.

AWUF Halt timing diagram

Figure 34.

AWUFH mode flowchart

WDGHALT is an option bit. See Section 15.1: Option bytes for more details.

Peripheral clocked with an external clock source can still be active.

Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external

interrupt). Refer to Table 17: Interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

AWUFH interrupt

fCPU

Run mode

Halt mode

256 or 4096 tCPU

Run mode

fAWU_RC

Clear

by software

tAWU

RESET

INTERRUPT (3)

CPU

MAIN OSC

PERIPHERALS (2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

OFF

XX (4)

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

XX (4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT (1)

WATCHDOG

RESET

CYCLE

AWU RC OSC

OFF

AWU RC OSC

OFF

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=1)

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