ST72344S2 datasheet(38/247 Pages) STMICROELECTRONICS

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Central processing unit

ST72344xx, ST2345xx

38/247

Doc ID 12321 Rev 6

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last

arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last

arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an

underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt management bits

Bits 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is

given by the corresponding bits in the interrupt software priority registers (IxSPR). They can

be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP

instructions.

See the interrupt management chapter for more details.

Table 6.

Interrupt software priority

Priority

Level 0 (main)

Level 1

Level 2

Level 3 (= interrupt disable)

ST72344S2 数据表(PDF) 38 Page - STMicroelectronics

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