ST72344S2 datasheet(46/247 Pages) STMICROELECTRONICS

46 / 247 page

Supply, reset and clock management

ST72344xx, ST2345xx

46/247

Doc ID 12321 Rev 6

7.4.2

RC control register (RCCRL)

Reset value: 0000 0011 (03h)

Bits 7:2 = Reserved, must be kept cleared.

Bits 1:0 = CR[1:0] RC Oscillator Frequency Adjustment Bits

This 10-bit value must be written immediately after reset to adjust the RC oscillator

frequency in order to obtain the specified accuracy. The application can store the

correct value for each voltage range in EEPROM and write it to this register at startup.

0000h = maximum available frequency

03FFh = lowest available frequency

Note:

To tune the oscillator, write a series of different values in the register until the correct

frequency is reached. The fastest method is to use a dichotomy starting with 200h.

7.5

Reset sequence manager (RSM)

7.5.1

Introduction

The reset sequence manager includes three reset sources as shown in Figure 16:

●

External RESET source pulse

●

Internal LVD reset (low voltage detection)

●

Internal watchdog reset

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1: Illegal opcode reset on page 196 for further details.

These sources act on the RESET pin and it is always kept low during the delay phase.

The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic reset sequence consists of 3 phases as shown in Figure 15:

●

Active phase depending on the reset source

●

256 or 4096 CPU clock cycle delay (selected by option byte)

●

reset vector fetch

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay

should be selected by option byte to correspond to the stabilization time of the external

oscillator used in the application (see Section 15.1: Option bytes).

The reset vector fetch phase duration is 2 clock cycles.

000

CR1

CR0

Read/Write

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