TP3410J datasheet(3/32 Pages) NSC

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Pin Descriptions (Continued)

PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE

ONLY (MWe1)

Symbol

Description

2Lia

Receive 2B1Q signal differential inputs

3Lib

from the line transformer For normal full-

duplex operation these pins should be

connected to the Log pins through the

recommended coupling circuit as shown

in the Applications section

The MicrowireGCI Select pin which must

be tied to VCCD to enable the Microwire

Interface with any of the data formats at

the Digital System Interface

BCLK

The Bit Clock pin which determines the

data shift rate for ‘B’ and ‘D’ channel data

on the digital interface side of the device

When Digital System Interface (DSI) Slave

mode is selected (see Digital Interfaces

section) BCLK is an input which may be

any multiple of 8 kHz from 256 kHz to

4096 MHz It need not be synchronous

with MCLK

When DSI Master mode is selected this

pin is a CMOS output clock at 256 kHz

512 kHz 1536 MHz 2048 MHz or 256

MHz depending on the selection in Com-

mand Register 1 It is synchronous with

the data on Bx and Br

FSa

In DSI Slave mode this pin is the Transmit

Frame Sync pulse input requiring a posi-

tive edge to indicate the start of the active

channel time for transmit B1 channel data

into Bx In DSI Master mode this pin is a

Frame Sync CMOS output pulse conform-

ing with the selected Digital Interface for-

mat

FSb

In DSI Slave mode this pin is the Receive

Frame Sync pulse input requiring a posi-

tive edge to indicate the start of the active

channel time of the device for receive B

channel data out from Br (see DSI Format

section) In DSI Master mode this pin is a

Frame Sync CMOS output pulse conform-

ing with the selected Digital Interface for-

mat

The digital input for B and if selected D

channel data to be transmitted to the line

must be synchronous with BCLK

The TRI-STATE output for B and if select-

ed D channel data received from the line

it is synchronous with BCLK

The Microwire control channel data input

The Microwire control channel TRI-STATE

output for status information When not

enabled by CS this output is high-imped-

ance

Crystal specifications 1536 MHz g50 ppm parallel resonant RS s 20X

Load with 33 pF to GND each side (a7 pF due to pin capacitance)

Symbol

Description

CCLK

The Microwire control channel Clock input

which may be asynchronous with BCLK

The Chip Select input which enables the

Control channel data to be shifted in and

out when pulled low When high this pin

inhibits the Control interface

INT

The Interrupt output a latched open-drain

output signal which is normally high-im-

pedance

and goes low to indicate a

change of status of the loop transmission

system This latch is cleared when the

Status Register is read by the microproc-

essor

When the D-port is enabled this pin is the

digital input for D channel data to be trans-

mitted to the line clocked by DCLK or

BCLK see Register CR2 When the D-port

is disabled via CR2 this pin must be tied to

GND

When the D-port is enabled this pin is the

TRI-STATE output for D channel data to

be received from the line clocked by DCLK

or BCLK see Register CR2

DCLK

When the D-port is enabled in DSI Slave

or Master mode this is a 16 kHz clock

CMOS output for D channel data When

the D-port is disabled or not used this pin

must be left open-circuit

PIN DESCRIPTIONS SPECIFIC TO GCI MODE ONLY

(MWe0)

Symbol

Description

The MicrowireGCI select input

which

must be tied to GND to enable the GCI

mode at the Digital System Interface

The GCI MasterSlave select input for the

clock direction Connect this pin low to se-

lect BCLK and FSa as inputs ie

GCI

Slave Selection of LT or NT mode must

be made in register CR2 When MO is con-

nected high NT Mode is automatically se-

lected and BCLK FSa and FSb are out-

puts ie the GCI Master see Section 8

BCLK

The Bit Clock pin which controls the shift-

ing of data on the Bx and Br pins at a rate

of 2 BCLK cycles per data bit When GCI

Slave mode is selected (see Digital Inter-

faces section) BCLK is an input which

may be any multiple of 16 kHz from

512 kHz to 6144 MHz It need not be syn-

chronous with MCLK

When GCI Master mode is selected this

pin is a CMOS output clock at 512 kHz or

1536 MHz depending on the connection

of the S2CLS pin It is synchronous with

the data on Bx and Br

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