TP3410J datasheet(17/32 Pages) NSC

17 / 32 page

Functional Description (Continued)

90 COMMAND REGISTER FUNCTIONS

All addressing and bit-level functions are the same for both

the Microwire and GCI Monitor Channels except where not-

ed Register addresses are listed in Table II An asterisk

indicates the Power-on Reset state of each function The

device modes and Transmit M bits should be programmed

while the device is powered down

91 Writing to Command Registers

A command may be written to a register to modify its con-

tents by setting byte 1 bit 0e0 Registers CR1 2 3 OPR

and the Time-Slot Assignment registers may also be read-

back to verify the contents by addressing each register with

byte 1 bit 0e1 In Microwire Mode if the device has no data

waiting to be read during a command cycle it will return

X 0000 (No Change)

92 Reading Back Command Registers for Verification

To read back the current state of one of the write-able regis-

ters the appropriate readback command must first be load-

ed in via the control channel this will cause an interrupt to

be sent to the interrupt stack In Microwire mode the inter-

rupt must be serviced by a read cycle in which the com-

mand should be a NOP (or a new command) In this cycle

the previously addressed register is read back with byte 1

bit 0e1 In GCI mode the interrupt stack generates an au-

tonomous one-way message in the Monitor Channel If any

other interrupt conditions should occur during the readback

command cycle the readback result will be queued at the

bottom of the stack and will not generate its interrupt or

message until all other interrupts are cleared

93 Configuration Register CR1 Digital Interface

Byte 2

543

FF1

FF0

CK2

CK1

CK0

DDM

CMS

BEX

CR1 is set to X 00 at Power-On Reset

FF1 FF0 Digital System Interface Frame Format

Selection

These bits are effective in Microwire Mode only (MWe1)

They select the Digital Interface format as described in Sec-

tion 6

Format

FF1

FF0

CK0 – CK2 Digital Interface Clock Select

In Microwire Mode only and if DSI Master is selected (CMS

1) CK0 – CK2 bits select from a choice of 5 frequencies

for the BCLK output (In GCI Mode these bits have no ef-

fect) The frequency of 256 kHz is not valid with Format 4

CK2

CK1

CK0

BCLK Frequency

000

256 kHz Master

512 kHz Master

1536 kHz Master

2048 kHz Master

2560 kHz Master

DDM Delayed Data Mode Select

For Microwire mode see Section 61 FS Relationship to

Data In GCI Mode or Format 4 this bit has no effect

DDM e 0 for non-delayed data mode (see

Figure 11 )

DDM e 1 for delayed data mode (see

Figure 12 )

CMS DSI Clock MasterSlave Select

In Microwire Mode (MW e 1)

CMS e 0 for DSI Slave may be used in either LT or NT

Modes

CMS e 1 for DSI Master may be used in either LT or NT

Modes but when in LT Mode must also send X 1840 See

the TP3410 User’s Manual AN-913 Section 45 for details

In GCI Mode (MW e 0) this bit has no effect the MO pin

selects GCI Master or Slave

BEX B Channel Exchange

This command enables the two B channels to be ex-

changed as the data passes through the device between

the Digital Interface and the Line in both directions It should

not be used if any loopback is selected in the device

BEX e 0 for B channels mapped direct B1 to B1 and B2

to B2

BEX e 1 for B channels exchanged B1 to B2 and B2 to B1

94 Configuration Register CR2 Device Modes

Byte 2

SSS

NTS

DMO

DEN

BP1

BP2

CR2 is set to X 00 at Power-On Reset

SSS Superframe Synchronization Select

This bit is effective in LT mode only in NT mode the SFS pin

is an output When SSS e 0 SFS is an input which syn-

chronizes the transmit superframe counter on the line

When SSS e 1 SFS is an output superframe marker pulse

NTS NT or LT Select

NTS e 0 for LT Mode

NTS e 1 for NT Mode

DEN D Channel Port Select

When DEN e 0 the D channel port is disabled and the D

bits are transferred on the Br and Bx pins clocked by BCLK

The Dx pin must also be tied to GND for correct operation

When DEN e 1 the D channel port is enabled D bits are

transferred on the Dr and Dx pins in a mode selected by the

DMO bit see Section 63

DMO D Channel Transfer Mode Select

This bit is significant only when the D channel port is select-

ed (DEN bit e 1)

When DMO e 1 D channel data is shifted in and out on Dx

and Dr pins in a continuous mode at 16 kbits on the falling

and rising edges of DCLK respectively see

Figure 4

When DMO e 0 D channel data is shifted in and out on Dx

and Dr pins in a burst mode at the BCLK frequency when

the assigned time-slots are active see

Figure 5

DD 2BaD Data Disabling

When DD e 0 2BaD channel transfer is enabled as soon

as the line is completely synchronized

When DD e 1 B and D channel transfer is inhibited The

data transmitted to line is preset to send scrambled 1’s with

the device in NT mode or scrambled 0’s if the device is in LT

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