TABLE III Status Registers

Function

Byte 1 (Register Address)

Byte 2 (Data)

76543210

7

6

5

4

3

2

1

0

READABLE CONFIGURATION REGISTERS

Default (No Change

0

0000000

0

0

0

0

0

0

0

0

on a Write Cycle)

OPR Contents

0

0100001

CIE

EIE

FIE

OB1

OB0

OC1

OC0

0

CR1 Contents

0

0100011

FF1

FF0

CK2

CK1

CK0

DDM

CMS

BEX

CR2 Contents

0

0100101

SSS

NTS

DMO

DEN

DD

BP1

BP2

0

CR3 Contents

0

0100111

LB1

LB2

LBD

DB1

DB2

DBD

TLB

0

CR4 Contents

0

0101101

SH9

AACT

WS

333 Hz

saif

TFB0

RFS

LFS

TXB1 Contents

0

0110001

0

0

TS5

TS4

TS3

TS2

TS1

TS0

TXB2 Contents

0

0110011

0

0

TS5

TS4

TS3

TS2

TS1

TS0

RXB1 Contents

0

0110101

EB1

ED

TS5

TS4

TS3

TS2

TS1

TS0

RXB2 Contents

0

0110111

EB2

0

TS5

TS4

TS3

TS2

TS1

TS0

TXD Contents

0

0111001

DX5

DX4

DX3

DX2

DX1

DX0

SX1

SX0

RXD Contents

0

0111011

DR5

DR4

DR3

DR2

DR1

DR0

SR1

SR0

BEC1 (Note 2)

0

1000111

ec7

ec6

ec5

ec4

ec3

ec2

ec1

ec0

REGISTERS WHICH GENERATE A MICROWIRE INTERRUPT OR GCI MONITOR CHANNEL MESSAGE

(Note 4)

RXM4

0

1000000

M41

M42

M43

M44

M45

M46

M47

M48

RXM56 Spare Bits

0

1000010

0

ES2

ES1

M51

M61

M52

RFB

NEB

ACT Indication Reg

0

1000100

0

0

0

0

C4

C3

C2

C1

BEC1 (Note 2)

0

1000110

ec7

ec6

ec5

ec4

ec3

ec2

ec1

ec0

RX EOC Register

0

1

0

1

ea1

ea2

ea3

dm

ei1

ei2

ei3

ei4

ei5

ei6

ei7

ei8

(Note 3)

Note 1

Bit 7 of byte 1 is always the first bit clocked into the device

Note 2

BEC1 may be polled via the appropriate read command (see Table II) at any time to read the current error count

Note 3

In the Rx EOC Register

Note 4

Changes in contents of these registers are queued on a stack which generates interrupts or messages in the following priority order

1 Register Readback request

2 ACT Indication Register (Microwire only)

3 RXM4 Register

4 RX EOC Register

5 RXM56 Spare Bits Register

6 BEC1 Register

16