TLH9151

September 1994

TP3410 ISDN Basic Access

Echo-Cancelling 2B1Q U Transceiver

General Description

The TP3410 is a complete monolithic transceiver for ISDN

Basic Access data transmission at either end of the U inter-

face Fully compatible with ANSI specification T1601 it is

built on National’s advanced double-metal CMOS process

160 kbps full-duplex transmission on a single twisted-pair is

provided with user-accessible channels including 2 ‘B’

channels each at 64 kbps 1 ‘D’ channel at 16 kbps and an

additional 4 kbps for loop maintenance 12 kbps of band-

width is reserved for framing 2B1Q Line coding is used in

which pairs of binary bits are coded into 1 of 4 quantum

levels for transmission at 80k symbolssec (hence 2 Binary

1 Quaternary) To meet the very demanding specifications

talk the device includes 2 Adaptive Digital Signal Proces-

sors 2 Digital Phase-locked Loops and a controller for auto-

matic activation

The digital interface on the device can be programmed for

compatibility with either of two types of control interface for

chip control and access to all spare bits In one mode a

Microwire serial control interface is used together with a

vision Multiplexed format of PCM Combo devices and back-

planes This mode allows independent time-slot assignment

for the 2 B channels and the D channel

Alternatively the GCI (General Circuit Interface) may be se-

control spare bits and loop maintenance data on 4 pins

Features

Y

Y

Meets ANSI T1601 US Standard

Y

2B1Q line coding with scramblerdescrambler

Y

Range exceeds 18 kft of

26 AWG

Y

l

70 dB adaptive echo-cancellation and equalization

Y

On-chip timing recovery no precision external

components

Y

Direct connection to small line transformer

Y

Automatic activation controller

Y

Selectable digital interface formats

TDM with time-slot assigner up to 64 slots plus

GCI (General Circuit Interface) or

IDL (Inter-chip Digital Link)

Y

Backplane clock DPLL allows free-running XTAL

Y

Elastic data buffers meet Q502 wanderjitter for Slave-

slave mode on PBX Trunk Cards and DLC

Y

EOC and spare bits access with automatic validation

Y

Block error counter

Y

6 loopback test modes

Y

Y

20 mW idle mode with line signal ‘‘wake-up’’ detector

Applications

Y

LT NT-1 NT-2 Trunks U-TE’s Regenerators etc

Y

Digital Loop Carrier

Y

POTS Pair-Gain Systems

Y

Easy Interface to

Line Card Backplanes

‘‘S’’ Interface Device

TP3420A

CodecFilter Combos

TP30547 and TP30756

LAPD Processor

MC68302 HPC16400

HDLC Controller

TP3451

Combo and TRI-STATE are registered trademarks of National Semiconductor Corporation

The General Circuit Interface (GCI) is an interface specification of the Group-of-Four Euro-

pean Telecommunications Companies

Block Diagram

TLH9151 – 1

Note

Pin names show Microwire mode

C1995 National Semiconductor Corporation

RRD-B30M115Printed in U S A