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PIMB063T-R68MS-63 数据表(PDF) 15 Page - Texas Instruments

部件名 PIMB063T-R68MS-63
功能描述  22-V Input, 10-A Integrated FET Converter With Ultra-Low Quiescent ( ULQ)
PDF  29 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

PIMB063T-R68MS-63 数据表(HTML) 15 Page - Texas Instruments

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OUT
SS
SLEW
SLEW
V
t
C
I
=
´
TPS51362
www.ti.com
SLUSBB6A – FEBRUARY 2013 – REVISED JUNE 2013
Power Sequences: Soft-Start and Power Good
Prior to asserting EN high, the power stage conversion voltage and V5IN voltage should be up and running.
When EN is asserted high, TPS51362 provides soft start operation to suppress in-rush current during startup.
The soft start action is achieved by an internal SLEW current of 10 µA (typ) sourcing into a small external MLCC
capacitor connected from SLEW pin to GND.
Use Equation 4 to determine the soft-start timing.
where
CSLEW is the soft-start capacitance
VOUT is the output voltage
ISLEW is the internal, 10-µA current source
(4)
The TPS51362 includes a PGOOD open drain output. During the startup, once the output voltage is slewing up
within –8% of the final setpoint target, the PGOOD becomes asserted after 1.5 ms of delay from the end of the
soft-start period. During the operation, if the output voltage rises beyond 120% (typ) of the setpoint, the PGOOD
pin becomes immediately de-asserted without hysteresis. Re-asserting the PGOOD pin requires either resetting
either the V5IN pin or the EN pin. If the output voltage falls below 68% (typ) of the setpoint, the PGOOD pin
becomes immediately de-asserted without hysteresis. Re-asserting the PGOOD pin requires resetting either the
V5IN pin or the EN pin.
Fault Protection
Overcurrent Limit
TPS51362 integrates both high side and low side FETs to support a maximum DC current of 10-A operation. The
current sensing method employed for over current limit is to monitor the SW node during the “ON” state of the
low side FET for each switching cycle. TRIP pin is used to program one of the two current limits for TPS51362
operation (see Table 3). When the overcurrent limit is detected, the converter does not allow the next “ON” cycle
for the high side FET until the overcurrent limit is no longer reached. This ensures the safe operation of the
converter. And when the overcurrent limit condition persists, the current to the load exceeds the current to the
output capacitors, the output voltage tends to fall. When the output voltage falls below the undervoltage
protection threshold, the converter latch shut down.
Table 3. TRIP Pin Settings
TYPICAL OCL
TRIP
LIMIT IOCL (A)
GND
8
5V
12
Negative Overcurrent Limit
TPS51362 is also protected by the negative over current limit. Both positive and negative current limit is
programmed by the TRIP pin. Negative current limit level is the same as that of positive current limit level (see
Table 3). During the normal converter operation, negative current is not allowed due to the mandatory light load
operation for this device (Auto Skip). It is during the OOB or OVP operation, negative overcurrent might be
engaged.
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: TPS51362



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