PIMB063T-R68MS-63 datasheet(17/29 Pages) TI1

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SLEW

OUT

10 nF

(

)

(

)

OUT

P P

1.05V

19.5 V

1.05 V

800 kHz

19.5 V

0.68 H

1.8 A

TPS51362

www.ti.com

SLUSBB6A – FEBRUARY 2013 – REVISED JUNE 2013

DESIGN PROCEDURE

Introduction

The simplified design procedure is done for a VCCIO rail for Intel platform application using TPS51362.

Step One: Determine the system specifications.

The VCCIO rail requirements provide the following key parameters:

•

VOUT = 1.05 V

•

ICC(max) = 6 A

•

IDYN(max) = 4 A

Step Two: Determine the power supply design specifications.

The input voltage range and operating frequency are of primary interest. For this example:

•

7.4 V

≤ VIN ≤ 19.5 V

•

fSW = 800 kHz

Step Three: Set the output voltage.

TPS51362 supports resistor-less fixed voltage operation by the use of both REFIN and REFIN2 pins (see

Table 1). Grounding both REFIN and REFIN2 pins provides a 1.05-V fixed output setpoint.

Step Four: Determine inductance value and choose inductor.

Smaller values of inductor have better transient performance and smaller physical size but higher ripple and

lower efficiency. Higher values have the opposite characteristics. It is common practice to limit the ripple current

to 25% to 50% of the maximum current. For this example,use 30% as a starting point. IL(P-P)= 6 A × 0.30 = 1.8 A.

For a switching frequency of 800 kHz, maximum 19.5-V input and 1.05-V output.

(5)

For this application, a 0.68-µH, 6.8 mm × 7.3 mm × 3.0 mm inductor with typical DCR of 4.8 m

Ω and heating

current of 16 A is chosen. The Cyntec part number of the inductor is PIMB063T.

Step Five: Calculate SLEW capacitance.

The SLEW pin is used to program the soft-start time. During soft-start operation, the current source used to

program the SLEW rate is 10 µA (typ). In this design example, the soft-start timing should be target to be in the

range of 500 µs to 2 ms. The proper slew rate design minimizes large inductor current perturbation during the

startup, thus reducing the possibility of acoustic noise in the system.

(6)

•

ISLEW = 10 µA,

•

dt = tSS = 1 ms

•

ΔVOUT = 1.05 V

Step Six: Select the proper OCL.

There are two options for the over current limit (see Table 3). For this application example, because ICC(max) =

6 A, the proper OCL level should be set at least 30% over the ICC(max) level, which makes the 8-A OCL

appropriate for this design. Grounding the TRIP pin achieves this effect.

Step Seven: Determine the output capacitance.

The amount of the output capacitance needed for this design is both a function of loop stability and of transient

requirement.

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