CS5372 datasheet(13/22 Pages) CIRRUS

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CS5371/CS5372

DS255PP2

and C is the internal sampling capacitor.

2.048 MHz MCLK yields a voltage reference input

impedance

approximately

[1 / (2.048 MHz)*(20 pF)], or about 24 kohms.

6.3.

Gain Accuracy

Gain accuracy of the CS5371/CS5372 modulators

is affected by variation of the voltage reference in-

put. A change in the voltage reference input im-

pedance due to a change in MCLK could affect

gain accuracy when using the higher source imped-

ance configuration of Figure 6. The VREF+ pin in-

put impedance and the external low-pass filter

resistor create a resistive voltage divider for the

output reference voltage, reducing the effective

voltage reference input. If gain error is to be mini-

mized, especially when MCLK is to be changed,

the voltage reference should have a low output im-

pedance to minimize the effect of the resistive volt-

age divider.

The buffered voltage reference

configuration of Figure 7 offers lower output im-

pedance and more stable gain characteristics.

6.4.

Gain Drift

Gain drift of the CS5371/CS5372 modulators due

to temperature is around 5 ppm/°C, and does not in-

clude the temperature drift characteristics of the ex-

ternal voltage reference. Gain drift is not affected

by the modulator sample rate or by power supply

variations.

7. DIGITAL FILTER INTERFACE

The CS5371/CS5372 modulators are designed to

operate with the CS5376 digital filter. The CS5376

generates the modulator clock and synchronization

signal inputs (MCLK and MSYNC), while receiv-

ing the modulator data and over-range flag outputs

(MDATA and MFLAG). The modulators produce

an oversampled

∆−Σ serial bit stream at 512 kbits

per second when operated from a 2.048 MHz mod-

ulator clock.

7.1.

Modulator Clock - MCLK

For proper operation, the CS5371/CS5372 modula-

tors must be provided with a CMOS compatible

clock on the MCLK pin. MCLK is internally divid-

ed by four to generate the modulator sampling

clock. MCLK must have less than 300 ps of in-

band jitter to maintain full performance specifica-

tions.

When used with the CS5376 digital filter, MCLK is

automatically

generated

and

typically

2.048 MHz or 1.024 MHz. MCLK can be generat-

ed by other means, using a crystal oscillator for ex-

ample, and can run any rate between 100 kHz and

2.2 MHz. If MCLK is disabled, the modulators are

placed into a micro-power state.

They are

equipped with loss of clock detection circuitry to

force power down if MCLK is removed.

The choice of MCLK frequency affects the perfor-

mance of the CS5371/CS5372 modulators. They

exhibit the best dynamic range (SNR) performance

with faster MCLK rates because of increased over-

sampling of the analog input signal. The modula-

tors exhibit the best total harmonic distortion

(THD) performance with slower MCLK rates be-

cause slower sampling allows more time to settle

the analog input signal.

7.2.

Modulator Data - MDATA

The CS5371/CS5372 modulators output a

∆−Σ se-

rial bitstream to the MDATA pin, with a one’s den-

sity proportional to the amplitude of the analog

input signal and a bit rate determined by the modu-

lator sampling clock.

The modulator sampling

clock is a divide by four of MCLK, so for a

2.048 MHz MCLK the modulator sampling clock

and MDATA output bit rate will be 512 kHz.

The MDATA output has a one’s density defined as

nominal 50% for no signal input, 86% for positive

full scale, and 14% for negative full scale. It has a

maximum positive over-range capability to 93%

and a maximum negative over-range capability to

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