CS5371/CS5372

4

DS255PP2

Notes: 8. The upper bandwidth limit is determined by the CS5376 digital filter. A simple single pole anti-alias filter

with a -3 dB frequency at (MCLK / 256) should be placed in front of each channel.

9. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram,

and applies to signal frequencies from DC to the stop-band frequency selected in the CS5376.

10. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.

11. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the

signal bandwidth by a factor of 2.

12. Tested with a 100 mVp-p sine wave applied separately to each supply.

Parameter

Symbol

Min

Typ

Max

Unit

Specified Temperature Range

-40

-

+85

°C

Input Characteristics

Input Signal Frequencies

(Note 8)

BW

DC

-

1644

Hz

Input Voltage Range

(Note 9)

VIN

-

-

5

Input Over-range Voltage Tolerance

(Note 9)

5-

-

%F.S.

Input Signal plus Common Mode

VA-

-

VA+

V

Common Mode Rejection Ratio

CMRR

-

90

-

dB

Channel Crosstalk, CS5372 only

CXT

-

-120

-

dB

Voltage Reference Input

VREF

(VREF+) - (VREF-)

-

2.5

-

V

VREF Current

-

-

120

µA

Power Supplies

DC Power Supply Currents

(Note 10 and 11)

LPWR = 0; MCLK = 2.048 MHz

Analog

Digital

LPWR = 1; MCLK = 1.024 MHz

Analog

Digital

VA

VD

VA

VD

-

-

-

-

5.0

0.1

3.0

0.1

7.0

0.2

4.5

0.2

mA

mA

mA

mA

Power Down

CS5371

PWDN = 1

PWDN = 1, MCLK = 0

CS5372

PWDN1 or PWDN2 = 1

PWDN1 = PWDN2 = 1

PWDN1 = PWDN2 = 1; MCLK = 0

-

-

-

-

-

1

10

25

1

10

-

-

-

-

-

mW

µW

mW

mW

µW

Power Supply Rejection

DC - 128 kHz

(Note 12)

PSRR

-

90

-

dB