CS5372 datasheet(20/22 Pages) CIRRUS

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CS5371/CS5372

DS255PP2

INF1-, INF2- _ Channel 1 & 2 Fine Inverting Input, pin 3, 10

Fine inverting analog inputs.

VREF+ _ Positive Voltage Reference Input, pin 5

Input for an external +2.5V voltage reference relative to VREF-.

VREF- _ Negative Voltage Reference Input, pin 6

This pin must be tied to VA-.

Digital Inputs

MCLK _ Modulator Clock Input, pin 19

A CMOS compatible clock input for the modulator internal master clock, nominally 2.048

MHz with an amplitude equal to the VD digital power supply.

MSYNC _ Modulator Sync Input, pin 20

A low to high transition resets the internal clock phasing of the modulator. This assures the

sampling instant and modulator data output are synchronous to the external system.

OFST _ Offset Mode Select, pin 14

When high, adds approximately +100mV of offset to the analog inputs to guarantee any zero

input

∆−Σ idle tones are removed. When low, no offset is added.

LPWR _ Low Power Mode Select, pin 23

When set high with MCLK operating at 1.024 MHz, modulator power dissipation is reduced to

15 mW per channel.

PWDN1, PWDN2 _ Channel 1 & 2 Power-down Mode, pin 24, 13

When high, the modulator is in power down mode and consumes 1mW. Halting MCLK while

in power down mode reduces modulator power dissipation to 10 µW.

Digital Outputs

MDATA1, MDATA2 _ Modulator Data Output, pin 21, 16

Modulator data is output as a 1-bit serial data stream at a 512 kHz rate with an MCLK input of

2.048 MHz. Modulator data is output at a 256 kHz rate with an MCLK input of 1.024 MHz.

MFLAG1, MFLAG2 _ Modulator Flag, pin 22, 15

A high level output indicates the modulator is unstable due to an over-range on the analog

inputs.

CS5372 数据表(PDF) 20 Page - Cirrus Logic