9/36

L9634

Additional capacitance during the disable time test erroneously extends the measured output disable time, and minimum capaci-

tance on MISO is the worst case for output hold time.

Figure 6. SPI Timing Diagram

Table 6. SPI Timing (All SPI timing is performed with a 200pF load on MISO unless otherwise noted)

Item

Symbol

Parameter

Limits

Min

Max

Unit

-

fop

Transfer Frequency

dc

5.50

MHz

SCLK Period

181

-

ns

Enable Lead Time

65

-

ns

Enable Lag Time

50

-

ns

SCLK High Time

65

-

ns

SCLK Low Time

65

-

ns

MOSI Input Setup Time

20

-

ns

MOSI Input Hold Time

20

-

ns

MISO Access Time

-

66

ns

MISO Disable Time (Note 1)

-

100

ns

10

MISO Output Valid Time

-

45

ns

11

MISO Output Hold Time (Note 1)

0

-

ns

12

Rise Time (Design Information)

-

30

ns

13

Fall Time (Design Information)

-

30

ns

14

CS Negated Time

100

-

ns

Obsolete

Product(s)

- Obsolete

Product(s)