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4.25 Register Mode

Register mode message is defined as shown in table below.

Table 12. MOSI Register Mode Message Definition

When bit D13 is set to '1,' OSD writes the data-bit to its internal register. The address bit desig-nates a

specific register in OSD. This address-bit is defined as shown below.

When the ADC resistance measurement is addressed, OSD ignores the data-bit. Upon the detection of

this ADC resistance measurement on the address-bit, OSD sends the 8-bit resistance measurement value

in the register mode response.

A write request contains valid mode bits, bit D13 set to '1,' valid address bits and valid data bits. In the next

valid CS, a register mode response contains the valid register content and not the echo from previous

command.

A read request contains valid mode bits, bit D13 set to '0,' and valid address bits. The data bits will be

ignored by the OSD. In the next valid CS, a register mode response contains a valid register content. This

register is determined by the address bits sent in the previous command.

Bit

State

Description

D15

0

Mode Bits

D14

0

D13

0

Read Configuration Register

1

Write Configuration Register

D12

Address-bit

D11

D10

D9

D8

D7

Data-bit

D6

D5

D4

D3

D2

D1

D0

Table 13. Address-bit Definition

Bit D12

Bit D11

Bit D10

Bit D9

Bit D8

Description

RES

ADC

DIAG

AD1

AD0

Program Other Options

0

0

0

0

0

STATUS.FLT Configuration Register

0

0

0

0

1

Deployment Configuration 1 Register

0

0

0

1

0

Deployment Configuration 2 Register

000

1

1

Soft Reset

RES

ADC

DIAG

AD1

AD0

Diagnostic Fault Registers

0

0

1

0

0

Channel 0 and 1 Register (see table 18)

0

0

1

0

1

Channel 2 and 3 Register, Table 19

0

0

1

1

0

Channel 4 and 5 Register (see table 20)

Obsolete

Product(s)

- Obsolete

Product(s)