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SPI transfer. OSD ignores all SPI transfers, which are not a 16-bit transfer and issue a SPI fault response

in the next valid CS.

4.20 Serial Clock (SCLK)

The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has TTL level

compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.

When CS is asserted, both the SPI master and this device latch input data on the rising edge of SCLK.

The SPI master typically shifts data out on the falling edge of SCLK, as does this device.

4.21 Serial Data Output (MISO)

The MISO output pin is in a tri-state condition when CS is negated. When CS is asserted, the MSB is the

first bit of the word transmitted on MISO and the LSB is the last bit of the word transmitted on MISO. This

pin supplies a "rail to rail" output, so if interfaced to a microprocessor that is using a lower VDD supply,

the appropriate microprocessor input pin shall not sink more than IOH and shall not clamp the MISO volt-

4.22 Serial Data Input (MOSI)

The MOSI input takes data from the master microprocessor while CS is asserted. The MSB is the first bit

of each word received on MOSI and the LSB is the last bit of each word received on MOSI. This pin has

TTL level compatible input voltages allowing proper operation with micro-processors using a 3.3 to 5.0 volt

supply.

4.23 SPI Transmission

The SPI provides access to read/write to the registers internal to OSD. OSD responses to various com-

mands summarized in the below table. OSD response to the previous command is sent in the next valid CS.

Table 10. OSD SPI Response

4.24 SPI Bit Definition - MOSI Bit

Figure 22. MOSI Bit Layout

Table 11. MOSI Mode Bits Definition

Mode Bits

MOSI Command

Mode Bits

MISO Response

D15

D14

D15

D14

0

0

Register Mode

0

0

Register Mode

0

1

Command Mode

0

1

Command Mode

1

0

Diagnostic Mode

1

1

Status Response

1

1

Monitor Mode

1

1

Status Response

X

X

SPI Transmission Fault

1

0

SPI Fault Response

Bit D15

Bit D14

Description

0

0

Register Mode

0

1

Command Mode

1

0

Diagnostic Mode

1

1

Monitor Mode

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MSB

LSB

Obsolete

Product(s)

- Obsolete

Product(s)