| 数据搜索系统,热门电子元器件搜索 |
|
STR710FZ1 数据表(PDF) 77 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STR710FZ1 数据表(HTML) 77 Page - STMicroelectronics |
|
77 / 80 page ![]() STR71xFxx STR710RZ Known limitations Doc ID 10350 Rev 13 77/80 8 Known limitations Description If an IRQ or FIQ interrupt is pending and the Interrupt vector register (EIC_IVR) is not yet read, the HALT bit in the RCCU_SMR register can not be written. Therefore a software reset can not be generated. Workaround To generate a software reset when an IRQ or FIQ line is pending, either: ● reset the EIC peripheral by setting bit 14 in the APB2_SWRES register, or ● read the EIC_IVR register prior to generating a software reset. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |