STR710FZ1 datasheet(25/80 Pages) STMICROELECTRONICS

25 / 80 page

STR71xFxx STR710RZ

System architecture

Doc ID 10350 Rev 13

25/80

Table 5.

STR711/STR712/STR715 pin description

Pin n°

Pin name

Input

Output

Main

function

(after

reset)

Alternate function

P0.10/U1.RX/

U1.TX/

SC.DATA

I/O

CT X 4mA T

Port 0.10

UART1:

Receive Data

input

UART1: Transmit data

output.

Note: This pin may be used for

Smartcard DataIn/DataOut or single

wire UART (half duplex) if programmed

as Alternate Function Output. The pin

will be tri-stated except when UART

transmission is in progress

P0.11/BOOT.1

/U1.TX

I/O

4mA

Port 0.11

Select Boot

Configuration

input

UART1: Transmit data

output.

P0.12/SC.CLK I/O

4mA

Port 0.12 Smartcard reference clock output

4VSS

Ground voltage for digital I/Os2)

P0.13/U2.RX/

T2.OCMPA

I/O

CT X 4mA X

Port 0.13

UART2:

Receive Data

input

Timer2: Output

Compare A output

P0.14/U2.TX/

T2.ICAPA

I/O

4mA

Port 0.14

UART2:

Transmit data

output

Timer2: Input Capture

A input

7BOOTEN

Boot control input. Enables sampling of BOOT[1:0]

pins

8VSS

Ground voltage for digital I/Os2)

9V33

Supply voltage for digital I/Os2)

JTDI

JTAG Data input. External pull-up required.

JTMS

JTAG Mode Selection Input. External pull-up

required.

JTCK

JTAG Clock Input. External pull-up or pull-down

required.

JTDO

8mA

JTAG Data output. Note: Reset state = HiZ.

JTRST

JTAG Reset Input. External pull-up required.

Reserved, must be forced to ground.

TEST

Reserved, must be forced to ground.

V33IO-PLL

Supply voltage for digital I/O circuitry and for PLL

reference2)

VSSIO-PLL

Ground voltage for digital I/O circuitry and for PLL

reference2)

Reference clock input

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