X5083

Characteristics subject to change without notice.

2 of 21

REV 1.1.6 6/25/02

www.xicor.com

DESCRIPTION

This device combines four popular functions, Power-on

Reset Control, Watchdog Timer, Supply Voltage Super-

vision, and Block Lock Serial EEPROM Memory in one

package. This combination lowers system cost, reduces

board space requirements, and increases reliability.

Applying power to the device activates the power on

reset circuit which holds RESET active for a period of

time. This allows the power supply and oscillator to sta-

bilize before the processor can execute code.

The Watchdog Timer provides an independent protection

mechanism for microcontrollers. When the microcontroller

fails to restart a timer within a selectable time out interval,

the device activates the RESET signal. The user selects

the interval from three preset values. Once selected, the

interval does not change, even after cycling the power.

user’s system from low voltage conditions, resetting

proper operating level and stabilizes. Five industry

unique circuits allow the threshold to be reprogrammed to

meet custom requirements or to fine-tune the threshold

for applications requiring higher precision.

PIN CONFIGURATION

PIN DESCRIPTION

Pin

(SOIC/

PDIP)

Pin

TSSOP

Name

Function

13

CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high

impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby

power mode. CS LOW enables the device, placing it in the active power mode. Prior to the

start of any operation after power up, a HIGH to LOW transition on CS is required.

Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The

absence of a HIGH to LOW transition within the watchdog time out period results in RESET

going active.

24

SO

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin.The

falling edge of the serial clock (SCK) clocks the data out.

57

SI

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data

on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes

(Table 1), addresses and data MSB first.

6

8

SCK

Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising

edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of

SCK changes the data output on the SO pin.

35

WP

Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited.

This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the

device operates normally.

46

Ground

82

Supply Voltage

7

1

RESET

CS remains either HIGH or LOW longer than the selectable watchdog time out period.

A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about

1V and remains active for 250ms after the power supply stabilizes.

SCK

SI

WP

CS/WDI

SO

1

2

3

4

8

7

6

5

8-Lead TSSOP

X5083

RESET

8-Lead SOIC, PDIP

X5083

CS/WDI

WP

SO

1

2

3

4

RESET

8

7

6

5

SCK

SI