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X5083P 数据表(PDF) 3 Page - Xicor Inc.

部件名 X5083P
功能描述  CPU Supervisor with 8Kbit SPI EEPROM
PDF  21 Pages
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制造商  XICOR [Xicor Inc.]
网页  http://www.xicor.com
标志 XICOR - Xicor Inc.

X5083P 数据表(HTML) 3 Page - Xicor Inc.

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X5083
Characteristics subject to change without notice.
3 of 21
REV 1.1.6 6/25/02
www.xicor.com
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5083 activates a power on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator.
RESET active also blocks communication to the device
through the SPI interface. When VCC exceeds the
device VTRIP value for 200ms (nominal) the circuit
releases RESET, allowing the processor to begin exe-
cuting code. While VCC < VTRIP communications to the
device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition and terminates any SPI communi-
cation in progress. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
When VCC falls below VTRIP, any communications in
progress are terminated and communications are
inhibited until VCC exceeds VTRIP for tPURST.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time
out period. The state of two nonvolatile control bits in the
status register determine the watchdog timer period. The
microprocessor can change these watchdog bits with no
action taken by the microprocessor these bits remain
unchanged, even after total power failure.
VCC Threshold Reset Procedure
The X5083 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X5083 threshold may be adjusted. The procedure is
described below, and uses the application of a high
voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher
voltage value. For example, if the current VTRIP is 4.4V
and the new VTRIP is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to
the programming voltage VP. Then send a WREN com-
mand, followed by a write of Data 00h to address 01h.
CS going HIGH on the write operation initiates the
VTRIP programming sequence. Bring WP LOW to com-
plete the operation.
Note: This operation also writes 00h to array address
01h.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value)
012 345 67
SCK
SI
CS
06h
012 345 67 89 10
20 21 22 23
16 Bits
0001h
02h
WP
VP = 15-18V
00h
WREN
Write
Address
Data



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