X5083P datasheet(5/21 Pages) XICOR

5 / 21 page

X5083

Characteristics subject to change without notice.

5 of 21

REV 1.1.6 6/25/02

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Figure 4. VTRIP Programming Sequence

VTRIP Programming

Apply 5V to VCC

Decrement VCC

RESET pin

goes active?

Measured VTRIP -

Desired VTRIP

DONE

Execute

Sequence

Reset VTRIP

Set VCC = VCC Applied =

Desired VTRIP

Execute

Sequence

Set VTRIP

New VCC Applied =

Old VCC Applied + Error

(VCC = VCC - 50mV)

Execute

Sequence

Reset VTRIP

New VCC Applied =

Old VCC Applied - Error

Error

≤ –Emax

–Emax < Error < Emax

YES

Error

≥ Emax

Emax = Maximum Desired Error

SPI Serial Memory

The memory portion of the device is a CMOS serial

EEPROM array with Xicor’s block lock protection. The

array is internally organized as x 8. The device features

a Serial Peripheral Interface (SPI) and software protocol

allowing operation on a simple four-wire bus.

The device utilizes Xicor’s proprietary Direct Write™

cell, providing a minimum endurance of 100,000 cycles

and a minimum data retention of 100 years.

The device is designed to interface directly with the

synchronous Serial Peripheral Interface (SPI) of many

popular microcontroller families.

The device monitors the bus and asserts RESET out-

put if the watchdog timer is enabled and there is no bus

activity within the user selectable time out period or the

supply voltage falls below a preset minimum VTRIP.

The device contains an 8-bit instruction register. It is

accessed via the SI input, with data being clocked in

on the rising edge of SCK. CS must be LOW during the

entire operation.

All instructions (Table 1), addresses and data are

transferred MSB ﬁrst. Data input on the SI line is

latched on the ﬁrst rising edge of SCK after CS goes

LOW. Data is output on the SO line by the falling edge

of SCK. SCK is static, allowing the user to stop the

clock and then start it again to resume operations

where left off.

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