ST8034P datasheet(25/39 Pages) STMICROELECTRONICS

25 / 39 page

Functional description

ST8034T, ST8034AT, ST8034P, ST8034C

26/40

DocID024587 Rev 4

6.3.2

ST8034P and ST8034C clock

In the case of ST8034P and ST8034C, only one external clock input (CLKIN) is

implemented, referred to VDD(INTF), with identical functionality such as use of the XTAL1 pin

in the case of ST8034T or ST8034AT.

6.4

Input and output circuits

When the I/O and I/OUC pins are pulled high by a 9 k

 resistor between I/O and VCC and/or

10 k

 resistor between I/OUC and VDD(INTF), both lines enter the idle state. The I/O pin is

referenced to VCC and the I/OUC pin to VDD(INTF), which allows operation at VCC level

different from VDD(INTF) level.

The first side on which a falling edge occurs becomes the master. An anti-latch circuit

disables falling edge detection on the other side, making it the slave. After a time delay tD,

the logic 0 present on the master side is sent to the slave side. When the master side

returns logic 1, the slave side sends logic 1 during time delay (tW(PU)). After this sequence,

both master and slave sides return to their idle states.

The active pull-up feature (one-shot circuit) ensures fast low to high transitions, making the

ST8034 outputs capable of delivering more than 1 mA, up to an output voltage of 0.9 VCC, at

a load of 80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the

internal pull-up resistor value and load current. The current sent to and received from the

card's I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.

6.5

Shutdown mode

After a power-on reset, if CMDVCC is high, the ST8034 device enters shutdown mode,

ensuring only the minimum number of circuits are active while the ST8034 device waits for

the microcontroller to start a session.



All card contacts are inactive. The impedance between the contacts and GND is

approximately 200





I/OUC pin is in high impedance with the 10 k

 pull-up resistor connected to VDD(INTF)



The voltage generators are stopped



The voltage supervisor is active



The internal oscillator runs at its low frequency (fOSC(INT)LOW).

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